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公开(公告)号：US20140329476A1
公开(公告)日：2014-11-06
申请号：US14258246
申请日：2014-04-22
Inventor： Shintaro YAMAMICHI , Hirokazu HONDA , Masaki WATANABE , Junichi ARITA , Norio OKADA , Jun UENO , Masashi NISHIMOTO , Michitaka KIMURA , Tomohiro NISHIYAMA
CPC classification number: H04W84/18 , H01L2224/45144 , H01L2224/48091 , H01L2224/49111 , H01L2924/00014 , H01L2924/00
Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
Abstract translation: 作为使用传感器的无线通信系统的组成要素的小型电子设备。 该器件的第一个特征是第一半导体芯片以芯片的形式裸地安装在第一布线板的前表面上，并且第二半导体芯片裸地安装在第二布线板上 芯片的形式。 第二特征是分别安装配置模块的无线通信单元和数据处理单元。 第三特征是第一和第二布线板沿板厚度方向堆叠以组成模块（电子设备）。
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公开(公告)号：US20250159363A1
公开(公告)日：2025-05-15
申请号：US18925421
申请日：2024-10-24
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA , Isao NAGAYOSHI
Abstract: A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
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公开(公告)号：US20250149100A1
公开(公告)日：2025-05-08
申请号：US18938668
申请日：2024-11-06
Applicant: Renesas Electronics Corporation
Inventor： Junichi SUZUKI , Atsunori MIKI
Abstract: A semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay is provided. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to respectively intersection points between the gate lines and the bit lines. The plurality of memory cells are connected to one gate line selected from among the plurality of gate lines respectively via the different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents in order to simultaneously perform writing into the plurality of memory cells.
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公开(公告)号：US12293925B2
公开(公告)日：2025-05-06
申请号：US17894579
申请日：2022-08-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yuki Murayama , Makoto Koshimizu , Takahiro Mori , Junjiro Sakai , Satoshi Iida
IPC: H01L21/4757 , H01L21/311 , H01L21/475 , H01L21/4763 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/522 , H01L23/532
Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.
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公开(公告)号：US20250142975A1
公开(公告)日：2025-05-01
申请号：US18915623
申请日：2024-10-15
Applicant: Renesas Electronics Corporation
Inventor： Yasuyuki MORISHITA , Koki NARITA , Satoshi MAEDA
Abstract: A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.
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Patent Agency Ranking
公开(公告)号：US12255596B2
公开(公告)日：2025-03-18
申请号：US18082762
申请日：2022-12-16
Applicant: Renesas Electronics Corporation
Inventor： Nishant Singh Thakur
Abstract: A filter circuit for use with a system configured to be coupled with an electrical load, the filter circuit comprising a first filter, wherein the first filter is configured to receive a first voltage and provide an output voltage, the output voltage being the first voltage after filtering by the first filter, and the filter circuit is configured to adjust the bandwidth of the first filter in response to a load transient.
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公开(公告)号：US20250079389A1
公开(公告)日：2025-03-06
申请号：US18799362
申请日：2024-08-09
Applicant: Renesas Electronics Corporation
Inventor： Yoshiharu SHIMIZU
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L23/13 , H01L23/498
Abstract: In plan view, an electrode pad of a semiconductor chip includes: a first region that contains a center of an exposed portion of the electrode pad; a second region that is located around the first region; and a third region that is located around the first region and that is located between the first region and the second region. Here, a first groove that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. The semiconductor substrate includes: a fourth region that overlaps with the third region but not overlaps with each of the first region and the second region, and a fifth region that overlaps with the first region but not overlaps with the third region. And, the first groove is formed in the semiconductor substrate at the fifth region but not at the fourth region.
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公开(公告)号：US12242402B2
公开(公告)日：2025-03-04
申请号：US17958685
申请日：2022-10-03
Applicant: Renesas Electronics Corporation
Inventor： Thorsten Hoffleit , Christian Mardmöller
IPC: G06F13/28
Abstract: A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.
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公开(公告)号：US12237254B2
公开(公告)日：2025-02-25
申请号：US17841196
申请日：2022-06-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keita Tsuchiya , Shuuichi Kariyazaki , Kazuhiro Mitamura
IPC: H01L23/498 , H01L23/14 , H01L23/36 , H01L23/367 , H01L23/66 , H01P3/08
Abstract: A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring. The first signal wiring is arranged in a region overlapping with a portion of a heat radiating plate. The second signal wiring is not arranged in the region. The ground plane has an opening portion located at a position overlapping with the first signal wiring. The opening portion is formed so as to extend along the first signal wiring.
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公开(公告)号：US20250055471A1
公开(公告)日：2025-02-13
申请号：US18798978
申请日：2024-08-09
Applicant: Renesas Electronics Corporation
Inventor： Tomohiko EBATA , Tetsuo MATSUI
Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.
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