Semiconductor device
    2.
    发明授权

    公开(公告)号:US10163791B2

    公开(公告)日:2018-12-25

    申请号:US15721784

    申请日:2017-09-30

    摘要: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.

    Semiconductor device having conductive patterns with mesh pattern and differential signal wirings

    公开(公告)号:US11990397B2

    公开(公告)日:2024-05-21

    申请号:US18163617

    申请日:2023-02-02

    IPC分类号: H01L23/498 H01L23/00

    摘要: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

    Semiconductor device
    6.
    发明授权

    公开(公告)号:US11049786B2

    公开(公告)日:2021-06-29

    申请号:US16575045

    申请日:2019-09-18

    摘要: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.

    Semiconductor device
    7.
    发明授权

    公开(公告)号:US10325841B2

    公开(公告)日:2019-06-18

    申请号:US16063280

    申请日:2016-02-10

    摘要: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.