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    Method Of Manufacturing High Electron Mobility Transistor
    4.
    发明申请
    Method Of Manufacturing High Electron Mobility Transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US20110212582A1

    公开(公告)日：2011-09-01

    申请号：US13017361

    申请日：2011-01-31

    Applicant: Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    Inventor： Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC: H01L21/335

    CPC classification number: H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    Abstract translation: 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

    Semiconductor structures including accumulations of silicon boronide and related methods
    5.
    发明申请
    Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
    半导体结构包括硅化硼的积累和相关方法

    公开(公告)号：US20070215959A1

    公开(公告)日：2007-09-20

    申请号：US11713877

    申请日：2007-03-05

    Applicant: Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    Inventor： Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    IPC: H01L29/94

    CPC classification number: H01L29/4941 ,  H01L21/28061

    Abstract: A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.

    Abstract translation: 半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。 绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。 绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。 第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。 还讨论了相关方法。

    Vertical channel field effect transistors having insulating layers thereon
    7.
    发明授权
    Vertical channel field effect transistors having insulating layers thereon 有权
    其上具有绝缘层的垂直沟道场效应晶体管

    公开(公告)号：US07148541B2

    公开(公告)日：2006-12-12

    申请号：US10780067

    申请日：2004-02-17

    Applicant: Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    Inventor： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC: H01L27/01

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

    Abstract translation: 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝向衬底延伸到源极/漏极 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

    SWITCHING ELEMENTS AND DEVICES, MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    SWITCHING ELEMENTS AND DEVICES, MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    切换元件和设备，存储器件及其制造方法

    公开(公告)号：US20130320286A1

    公开(公告)日：2013-12-05

    申请号：US13905822

    申请日：2013-05-30

    Applicant: Dong-soo LEE ,  Myoung-jae LEE ,  U-in CHUNG

    Inventor： Dong-soo LEE ,  Myoung-jae LEE ,  U-in CHUNG

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

    Abstract: A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer.

    Abstract translation: 开关元件包括：第一电极; 第二电极; 以及在所述第一电极和所述第二电极之间的含硅的仲氮化物层。 开关装置包括：第一电极和第二电极之间的阈值开关材料层。 阈值开关材料层包括阳离子金属元素，硫属元素，硅元素和氮元素。 存储器件包括：彼此平行布置的多个第一布线; 多个第二布线，穿过第一配线，彼此平行布置; 以及形成在所述多个第一布线和所述多个第二布线的每个交叉点处的存储单元。 存储单元包括具有含硅的恰氮氮化物层，中间电极和存储层的层压体。

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