公开(公告)号：US09305075B2

公开(公告)日：2016-04-05

申请号：US12474982

申请日：2009-05-29

Applicant: Justin H. Kuo ,  Hui-Lim Victor Lim

Inventor： Justin H. Kuo ,  Hui-Lim Victor Lim

IPC: G06F7/00 ,  G06F17/00 ,  G06F17/30

CPC classification number: G06F17/30595

Abstract: A mechanism by which rule attributes of varying types and numbers can be stored and searched in an efficient manner is provided by storing attribute values of each rule in a child table of a parent rule table. The child table is normalized and contains a foreign key pointing back to the parent rule table and has attribute-value pairs as table columns of the child table. Each rule is then represented by one row of the parent rule table and one or more corresponding rows of the child rule details table. A variable and unlimited number of attribute dimensions is supported among the rules, and search performance is improved through the use of database indexes on the rule details table attribute columns. Metadata representing the structure of the child rule details table will identify the data attributes for each dimension.

Abstract translation: 通过将每个规则的属性值存储在父规则表的子表中来提供可以以有效的方式存储和搜索不同类型和数字的规则属性的机制。 子表被归一化，并包含指向父规则表的外键，并将属性值对作为子表的表列。 然后，每个规则由父规则表的一行和子规则详细信息表的一个或多个相应行表示。 在规则中支持变量和无限数量的属性维度，通过在规则详细信息表属性列上使用数据库索引来提高搜索性能。 表示子规则详细信息表结构的元数据将标识每个维度的数据属性。

公开(公告)号：US06613648B1

公开(公告)日：2003-09-02

申请号：US10197354

申请日：2002-07-15

Applicant: Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

Inventor： Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

IPC: H01L21762

CPC classification number: H01L21/76224

Abstract: A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing process removes the polysilicon layer and forms a plug of dielectric material that fills the trench. The plug of dielectric material has a top surface that is planar with respect to the top of the silicon nitride layer.

Abstract translation: 浅沟槽隔离的方法和装置。 首先，在半导体衬底上沉积氮化硅层（SiN）。 然后在氮化硅层上沉积一层多晶硅。 在多晶硅层上沉积一层原硅酸四乙酯（TEOS）。 执行掩模和蚀刻步骤以形成延伸穿过TEOS层并穿过多晶硅层的开口。 然后执行蚀刻步骤以蚀刻多晶硅层的暴露的侧表面。 由此，多晶硅层的露出侧表面横向移动。 然后执行蚀刻步骤以形成延伸到半导体衬底中的沟槽。 介电材料被沉积成使得介电材料填充沟槽并填充延伸穿过多晶硅层和氮化硅层的开口。 然后使用化学机械抛光工艺抛光衬底。 化学机械抛光工艺去除多晶硅层并形成填充沟槽的电介质材料塞。 电介质材料的插塞具有相对于氮化硅层的顶部是平面的顶表面。

公开(公告)号：US07902548B2

公开(公告)日：2011-03-08

申请号：US11558079

申请日：2006-11-09

Applicant: Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

Inventor： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

IPC: H01L21/00

CPC classification number: G01R31/307 ,  G01R31/2853 ,  G01R31/2884

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract translation: 公开了集成电路和电子束测试方法。 集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。 描述了用于检测开路和短路的结构。

公开(公告)号：US20070085556A1

公开(公告)日：2007-04-19

申请号：US11558079

申请日：2006-11-09

Applicant: Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

Inventor： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

IPC: G01R31/02

CPC classification number: G01R31/307 ,  G01R31/2853 ,  G01R31/2884

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract translation: 公开了集成电路和电子束测试方法。 集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。 描述了用于检测开路和短路的结构。

公开(公告)号：US20060031267A1

公开(公告)日：2006-02-09

申请号：US10911803

申请日：2004-08-04

Applicant: Victor Lim ,  David Moore ,  F. Perry

Inventor： Victor Lim ,  David Moore ,  F. Perry

IPC: G06F17/30

CPC classification number: G06F11/1469 ,  G06F11/1471 ,  G06F2201/80

Abstract: An apparatus, system, and method are disclosed for efficient recovery of a database from a log of database activities. A log of database activities is filtered into a first sequential data set. The remainder portion of the log is sorted into a second sequential data set. The first sequential data set and the second sequential data set are merged and written to the database. Allowing the sequential records to bypass a sort operation reduces the amount of time and the system resource overhead required for database recovery.

Abstract translation: 公开了一种用于从数据库活动日志中有效地恢复数据库的装置，系统和方法。 数据库活动的日志被过滤到第一个顺序数据集中。 日志的剩余部分被排序成第二个顺序数据集。 第一个顺序数据集和第二个顺序数据集被合并并写入数据库。 允许顺序记录绕过排序操作可以减少数据库恢复所需的时间和系统资源开销。

公开(公告)号：US20060166402A1

公开(公告)日：2006-07-27

申请号：US11044282

申请日：2005-01-27

Applicant: Victor Lim ,  Fan Zhang ,  Jeffrey Lam

Inventor： Victor Lim ,  Fan Zhang ,  Jeffrey Lam

IPC: H01L21/48 ,  H01L23/48 ,  H01L21/50

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/76834 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02165 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05078 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13565 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.

Abstract translation: 实现了一种用于制造具有侧壁间隔物的新型高架结合焊盘结构的方法。 升高的焊盘结构在倒装芯片接合期间增加了芯片和衬底之间的空间。 间距增加导致更好的欠充，并减少芯片中的α粒子软错误。 侧壁间隔件将PbSn焊料凸块的润湿表面限制到接合焊盘的顶表面。 这导致较小的焊料凸块并且允许用于较高密度集成电路的焊盘阵列的更紧密的间隔。

公开(公告)号：US07052372B2

公开(公告)日：2006-05-30

申请号：US10014085

申请日：2001-12-13

Applicant: Seng-Keong Victor Lim ,  Paul Richard Proctor ,  Robert Chin Fu Tsai

Inventor： Seng-Keong Victor Lim ,  Paul Richard Proctor ,  Robert Chin Fu Tsai

IPC: B24B1/00

CPC classification number: B24B37/26 ,  B24B37/042 ,  B24B41/047 ,  B24D3/22

Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.

公开(公告)号：US06380106B1

公开(公告)日：2002-04-30

申请号：US09721719

申请日：2000-11-27

Applicant: Seng Keong Victor Lim ,  Young-way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

Inventor： Seng Keong Victor Lim ,  Young-way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

IPC: H01L2131

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/7682

Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the permeable dielectric layer.

Abstract translation: 一种制造具有通过汽化填料聚合物材料形成气隙的金属化方案的方法。 填充材料被临界可渗透的介电层覆盖。 该方法开始于在半导体结构上形成间隔的导线。 间隔的导线具有顶表面。 在间隔的导线和半导体结构之上形成填充材料。 填充材料优选由选自聚丙二醇（PPG），聚丁二烯（PB）聚乙二醇（PEG），氟化无定形碳和聚己内酯二醇（PCL）组成的组中的材料组成，并且通过旋涂工艺或 CVD工艺。 我们回蚀填充材料以暴露间隔的导线的顶表面。 接下来，将半导体结构加载到HDPCVD室中。 在关键步骤中，在填充材料上形成可渗透介电层。 可渗透介电层具有允许分解的气相填充材料扩散通过的性质。 在另一个关键步骤中，我们将填充材料蒸发成将填料材料变成气相填料。 气相填充材料通过可渗透的介电层扩散以在间隔的导线之间形成间隙。 在可渗透介电层上形成绝缘层。

公开(公告)号：US20110184681A1

公开(公告)日：2011-07-28

申请号：US12927411

申请日：2010-11-12

Applicant: Matthew P. Augustine ,  Stephen J. Harley ,  Victor Lim ,  Paul Stucky

Inventor： Matthew P. Augustine ,  Stephen J. Harley ,  Victor Lim ,  Paul Stucky

IPC: G06F17/18 ,  G01R27/28 ,  G01R23/00

CPC classification number: G01N22/00 ,  G01N27/221 ,  G01N33/00 ,  G01N33/14 ,  G01N33/146 ,  G01R33/12

Abstract: Methods, device and systems for identifying or fingerprinting an intact bottle of wine are provided. Such methods are useful in authenticating a bottle of wine.

Abstract translation: 提供了用于识别或指纹的完整瓶酒的方法，装置和系统。 这种方法在认证一瓶葡萄酒中是有用的。

公开(公告)号：US07160741B2

公开(公告)日：2007-01-09

申请号：US10703285

申请日：2003-11-06

Applicant: Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

Inventor： Seng-Keong Victor Lim ,  Dennis Tan ,  Tze Ho Simon Chan

IPC: H01L21/00

CPC classification number: G01R31/307 ,  G01R31/2853 ,  G01R31/2884

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract translation: 公开了集成电路和电子束测试方法。 集成电路包括具有接地栅格的测试结构，金属垫在其内具有空间并位于接地格栅内，金属线连接到接地格并定位在该空间中。 描述了用于检测开路和短路的结构。