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    MULTI-CHIPLET CLOCK DELAY COMPENSATION
    2.
    发明公开
    MULTI-CHIPLET CLOCK DELAY COMPENSATION 审中-公开

    公开(公告)号：US20240295898A1

    公开(公告)日：2024-09-05

    申请号：US18663864

    申请日：2024-05-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

    IPC: G06F1/08 ,  H03K5/00 ,  H03K5/22

    CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

    Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

    INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE
    8.
    发明申请
    INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE 有权
    用于训练存储器物理层接口的集成控制器

    公开(公告)号：US20150378603A1

    公开(公告)日：2015-12-31

    申请号：US14318114

    申请日：2014-06-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

    IPC: G06F3/06

    CPC classification number: G06F13/4072 ,  G06F13/1689

    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

    Abstract translation: 集成在存储器物理层接口（PHY）中的控制器可用于控制用于配置存储器PHY的训练以与诸如动态随机存取存储器（DRAM）的相关联的外部存储器进行通信，由此消除提供训练序列的需要 在BIOS和存储器PHY之间的数据流水线上。 例如，集成在存储器PHY中的控制器可以基于训练算法来控制用于与外部存储器通信的存储器PHY的读取训练和写入训练。 训练算法可以是无核训练算法，其收敛于存储器PHY和外部存储器之间的定时延迟和电压偏移的解，而不从基本输入/输出系统（BIOS）接收表征信号的种子信息 由训练序列生成的训练序列或命令所遍历的路径。

    MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE
    9.
    发明申请
    MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE 审中-公开
    用于分割通道架构的记忆系统组件

    公开(公告)号：US20140325105A1

    公开(公告)日：2014-10-30

    申请号：US13871437

    申请日：2013-04-26

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Edoardo Prete ,  Anwar Kashem ,  Brian Amick

    IPC: H01L23/538 ,  G06F13/16

    CPC classification number: G06F13/1642

    Abstract: In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request.

    Abstract translation: 在一种形式中，存储器模块包括包括第一等级并具有第一组和第二组以及第一和第二芯片选择导体的第一多个存储器件。 第一芯片选择导体互连第一组的每个存储器件的芯片选择输入端，并且第二芯片选择导体互连第二组的每个存储器件的芯片选择输入端。 在另一种形式中，系统包括存储器控制器，其响应于第一访问请求，使用数据总线的第一和第二部分以及第一和第二片选信号执行第一突发存取，并且使用所选择的一个进行第二突发存取 的数据总线的第一和第二部分以及响应于第二访问请求的第一和第二片选信号中的对应的一个。

    REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE
    10.
    发明申请
    REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE 有权

    公开(公告)号：US20240419343A1

    公开(公告)日：2024-12-19

    申请号：US18820442

    申请日：2024-08-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

    IPC: G06F3/06

    Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

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