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1.发明申请SELECTIVE INSERTION OF CLOCK MISMATCH COMPENSATION SYMBOLS IN SIGNAL TRANSMISSIONS 有权信号传输中时钟误差补偿符号的选择性插入公开(公告)号：US20140129867A1
公开(公告)日：2014-05-08
申请号：US13670086
申请日：2012-11-06
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gordon F. Caruk , Gerald R. Talbot
IPC: G06F1/00
Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.
Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。
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公开(公告)号：US20230308132A1
公开(公告)日：2023-09-28
申请号：US17705022
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Dean E. Gonzales , Edoardo Prete , Milam Paraschou , Mark Chirachanchai , Gerald R. Talbot
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage. The placement of the comparator and the ratio of the inductances of the inductors of the bridged T-coil circuit are based on whether the receiver includes self-diagnostic circuitry.
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公开(公告)号：US20230134926A1
公开(公告)日：2023-05-04
申请号：US17566199
申请日：2021-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/0175 , H03F3/45
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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公开(公告)号：US10698856B1
公开(公告)日：2020-06-30
申请号：US16223873
申请日：2018-12-18
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gordon Caruk , Gerald R. Talbot
Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.
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公开(公告)号：US10692545B2
公开(公告)日：2020-06-23
申请号：US16140356
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Balwinder Singh , Gerald R. Talbot , Alushulla Jack Ambundo , Edoardo Prete , Thomas H. Likens, III , Michael A. Margules
IPC: G11C7/10 , G11C5/14 , G11C11/4074 , H04L25/02 , H03K17/687
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
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Patent Agency Ranking
公开(公告)号：US20200098399A1
公开(公告)日：2020-03-26
申请号：US16140356
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Balwinder Singh , Gerald R. Talbot , Alushulla Jack Ambundo , Edoardo Prete , Thomas H. Likens, III , Michael A. Margules
IPC: G11C5/14 , H03K17/687 , H04L25/02 , G11C11/4074
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
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公开(公告)号：US10122392B2
公开(公告)日：2018-11-06
申请号：US15240549
申请日：2016-08-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Gerald R. Talbot , Dean E. Gonzales
Abstract: Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.
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公开(公告)号：US20170373944A1
公开(公告)日：2017-12-28
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US20170373788A1
公开(公告)日：2017-12-28
申请号：US15191322
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
CPC classification number: H04L1/0002 , H04L1/0073 , H04L1/244 , H04L7/0037 , H04L7/043 , H04L7/10 , H04L25/14 , H04L2012/5681
Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
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公开(公告)号：US12174769B2
公开(公告)日：2024-12-24
申请号：US17705048
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Gurunath Dollin , Edoardo Prete , Milam Paraschou , Edward Wade Thoenes , Ryan J. Hensley , Gerald R. Talbot
IPC: G06F13/40 , G06F1/08 , G06F1/12 , G06F13/42 , H03K19/173
Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.
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