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Patent Agency Ranking
公开(公告)号：US20180033482A1
公开(公告)日：2018-02-01
申请号：US15597709
申请日：2017-05-17
Inventor： Santosh Hariharan , Hieu Van Tran , Feng Zhou , Xian Liu , Steven Lemke , Nhan Do , Zhixian Chen , Xinpeng Wang
CPC classification number: G11C13/0011 , G11C11/00 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2013/0083 , G11C2013/0088 , G11C2013/0092 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/146
Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.
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公开(公告)号：US20130270508A1
公开(公告)日：2013-10-17
申请号：US13860870
申请日：2013-04-11
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor： Xiang LI , Navab Singh , Zhixian Chen , Xinpeng Wang , Guo-Qiang Patrick Lo
IPC: H01L45/00
CPC classification number: H01L45/1206 , B82Y10/00 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1675 , Y10S977/762 , Y10S977/84 , Y10S977/938
Abstract: According to embodiments of the present invention, a non-volatile memory device is provided. The non-volatile memory device includes a nanowire transistor including a nanowire channel, and a resistive memory cell arranged adjacent to the nanowire transistor and in alignment with a longitudinal axis of the nanowire channel. According to further embodiments of the present invention, a method of forming a non-volatile memory device is also provided.
Abstract translation: 根据本发明的实施例，提供了一种非易失性存储器件。 非易失性存储器件包括纳米线晶体管，其包括纳米线通道，以及与纳米线晶体管相邻并且与纳米线通道的纵向轴线对准布置的电阻存储器单元。 根据本发明的另外的实施例，还提供了一种形成非易失性存储器件的方法。
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公开(公告)号：US20210104659A1
公开(公告)日：2021-04-08
申请号：US16072965
申请日：2017-01-19
Applicant: Agency for Science, Technology and Research
Inventor： Hideaki Fukuzawa , Jun Yu , Michael Han , Xinpeng Wang , Vladimir Bliznetsov
Abstract: Various embodiments may provide a memory cell including a magnetic pinned layer with a substantially fixed magnetization direction, a crystalline spacer layer in contact with the magnetic pinned layer, and a magnetic storage layer. The magnetic storage layer may include an amorphous interface sub-layer in contact with the crystalline spacer layer, the amorphous interface sub-layer including a first alloy of iron (Fe) and at least one element. The amorphous storage layer may also include an amorphous enhancement sub-layer in contact with the amorphous interface sub-layer, the amorphous enhancement sub-layer including a second alloy of iron (Fe) and at least one element. The memory cell may additionally include a cap layer in contact with the amorphous enhancement sub-layer. A concentration of the at least one further element comprised in the first alloy and a concentration of the at least one further element comprised in the second alloy may be different.
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公开(公告)号：US09087975B2
公开(公告)日：2015-07-21
申请号：US13745993
申请日：2013-01-21
Applicant: Agency for Science, Technology and Research
Inventor： Xinpeng Wang , Xiang Li , Navab Singh , Guo-Qiang Patrick Lo
CPC classification number: H01L45/04 , B82Y10/00 , B82Y40/00 , H01L27/2409 , H01L27/2454 , H01L45/1226 , H01L45/1253 , H01L45/146 , H01L45/16 , Y10S977/762 , Y10S977/943
Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.
Abstract translation: 根据本发明的实施例，提供了一种电阻式存储装置。 电阻性存储器装置包括纳米线和包括电阻层的电阻性存储单元，该电阻层包括电阻变化材料，其中电阻层的至少一部分布置成覆盖纳米线表面的至少一部分，导电层 布置在电阻层的至少一部分上。 根据本发明的另外的实施例，还提供了形成电阻式存储装置的方法。
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公开(公告)号：US10276236B2
公开(公告)日：2019-04-30
申请号：US15597709
申请日：2017-05-17
Inventor： Santosh Hariharan , Hieu Van Tran , Feng Zhou , Xian Liu , Steven Lemke , Nhan Do , Zhixian Chen , Xinpeng Wang
Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.
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