公开(公告)号：US12218075B2

公开(公告)日：2025-02-04

申请号：US17566575

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hsu-Chiang Shih ,  Hung-Yi Lin ,  Chien-Mei Huang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.

公开(公告)号：US11798890B2

公开(公告)日：2023-10-24

申请号：US17584051

申请日：2022-01-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/105 ,  H01L25/162 ,  H01L25/165 ,  H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2225/107 ,  H01L2924/1434 ,  H01L2924/19102 ,  H01L2924/37001

Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section. The second signal transmission path is between the second surface of the sub-computing section and the at least one conductive via of the sub-computing section.

公开(公告)号：US11545427B2

公开(公告)日：2023-01-03

申请号：US16447839

申请日：2019-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Chien-Hua Chen ,  Teck-Chong Lee ,  Hung-Yi Lin ,  Pao-Nan Lee ,  Hsin Hsiang Wang ,  Min-Tzu Hsu ,  Po-Hao Chen

IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

公开(公告)号：US11348885B2

公开(公告)日：2022-05-31

申请号：US16732154

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H01L23/66 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.

公开(公告)号：US09997447B1

公开(公告)日：2018-06-12

申请号：US15618083

申请日：2017-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hung-Yi Lin ,  Sheng-Chi Hsieh

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.

公开(公告)号：US11824029B2

公开(公告)日：2023-11-21

申请号：US17374743

申请日：2021-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Han Chen ,  Hung-Yi Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  G02B6/30 ,  G02B6/42 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L24/17 ,  G02B6/30 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/17177

Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.

公开(公告)号：US11722220B2

公开(公告)日：2023-08-08

申请号：US17144938

申请日：2021-01-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Yu Lin ,  Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H04B10/00 ,  H04B10/40 ,  G02B6/42 ,  H04J14/00

CPC classification number: H04B10/40 ,  G02B6/4206 ,  G02B6/4257

Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.

公开(公告)号：US11296043B2

公开(公告)日：2022-04-05

申请号：US16703409

申请日：2019-12-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan Kung ,  Hung-Yi Lin ,  Chang-Yu Lin

IPC: H01L23/367 ,  H01L23/64 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.

公开(公告)号：US11201125B2

公开(公告)日：2021-12-14

申请号：US15442492

申请日：2017-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi Hsieh ,  Hung-Yi Lin ,  Cheng-Yuan Kung ,  Pao-Nan Lee ,  Chien-Hua Chen

IPC: H01L23/66 ,  H01L23/498 ,  H03H3/08 ,  H03H9/05 ,  H03H9/10 ,  H03H3/02 ,  H01L23/64

Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

公开(公告)号：US11189604B2

公开(公告)日：2021-11-30

申请号：US16653650

申请日：2019-10-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chao-Kai Hung ,  Chien-Wei Chang ,  Ya-Chen Shih ,  Hung-Jung Tu ,  Hung-Yi Lin ,  Cheng-Yuan Kung

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/00

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.