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    Power and ground design for through-silicon via structure
    1.
    发明授权
    Power and ground design for through-silicon via structure 有权

    公开(公告)号：US10600759B2

    公开(公告)日：2020-03-24

    申请号：US15404093

    申请日：2017-01-11

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chih-Pin Hung ,  Ying-Te Ou ,  Pao-Nan Lee

    IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L23/31

    Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

    Electronic device
    2.
    发明授权
    Electronic device 有权

    公开(公告)号：US11991827B2

    公开(公告)日：2024-05-21

    申请号：US17966701

    申请日：2022-10-14

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chun-Yen Ting ,  Pao-Nan Lee ,  Hung-Chun Kuo ,  Jung Jui Kang ,  Chang Chi Lee

    IPC: H05K1/14

    CPC classification number: H05K1/141

    Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.

    Semiconductor device and process of making the same
    5.
    发明授权
    Semiconductor device and process of making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09577027B2

    公开(公告)日：2017-02-21

    申请号：US14724522

    申请日：2015-05-28

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Teck-Chong Lee ,  Chien-Hua Chen ,  Yung-Shun Chang ,  Pao-Nan Lee

    IPC: H01L27/08 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L21/48 ,  H05K1/03 ,  H05K1/18 ,  H01L23/498

    CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

    Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

    Abstract translation: 半导体器件包括衬底，种子层，第一图案化金属层，电介质层和第二金属层。 种子层设置在基板的表面上。 第一图案化金属层设置在种子层上并具有第一厚度。 第一图案化金属层包括第一部分和第二部分。 电介质层设置在第一图案化金属层的第一部分上。 第二金属层设置在电介质层上，具有第二厚度，其中第一厚度大于第二厚度。 第一图案化金属层的第一部分，电介质层和第二金属层形成电容器。 第一图案化金属层的第一部分是电容器的下电极，第一图案化金属层的第二部分是电感器。

    Electronic device
    8.
    发明授权
    Electronic device 有权

    公开(公告)号：US12156336B2

    公开(公告)日：2024-11-26

    申请号：US17856898

    申请日：2022-07-01

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chiung-Ying Kuo ,  Hung-Chun Kuo ,  Pao-Nan Lee ,  Jung Jui Kang ,  Chang Chi Lee

    IPC: H05K1/18 ,  H05K1/02

    Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.

    Capacitor bank structure and semiconductor package structure
    10.
    发明授权
    Capacitor bank structure and semiconductor package structure 有权

    公开(公告)号：US11545427B2

    公开(公告)日：2023-01-03

    申请号：US16447839

    申请日：2019-06-20

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Yuan Kung ,  Chien-Hua Chen ,  Teck-Chong Lee ,  Hung-Yi Lin ,  Pao-Nan Lee ,  Hsin Hsiang Wang ,  Min-Tzu Hsu ,  Po-Hao Chen

    IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

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