摘要:
A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
摘要:
A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
摘要:
The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译:本发明提供具有高移动性和低界面电荷的栅堆叠结构,以及包括其的半导体器件,即金属氧化物半导体场效应晶体管(MOSFET)。 在半导体器件中,本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法,其中采用了高温退火工艺(大约800℃)。 在本发明中使用的高温退火提供了一种栅堆叠结构,其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少,约250cm 2 / Vs或更高的峰迁移率,并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解, 或更大。
摘要:
The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译:本发明提供具有高移动性和低界面电荷的栅堆叠结构,以及包括其的半导体器件,即金属氧化物半导体场效应晶体管(MOSFET)。 在半导体器件中,本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法,其中采用了高温退火工艺(约800℃)。 在本发明中使用的高温退火提供了一种栅堆叠结构,其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少,约250cm 2 / Vs或更高的峰迁移率,并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低, 或更大。
摘要:
The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译:本发明提供具有高迁移率和低界面电荷的栅叠层结构,以及包括其的半导体器件即金属氧化物半导体场效应晶体管(MOSFET)。 在半导体器件中,本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法,其中采用了高温退火工艺(大约800℃)。 本发明中使用的高温退火提供了一种栅极叠层结构,其具有约8×10 10电荷/ cm 2或更小的峰值迁移率,约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度,以及 在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。
摘要:
A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
摘要:
A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
摘要:
The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译:本发明提供具有高移动性和低界面电荷的栅叠层结构,以及包括其的半导体器件,即金属氧化物半导体场效应晶体管(MOSFET)。 在半导体器件中,本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。 本发明还提供一种制造本发明的栅叠层结构的方法,其中采用了高温退火工艺(大约800℃)。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度,约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。
摘要:
A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.
摘要:
The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.