公开(公告)号：US20060151846A1

公开(公告)日：2006-07-13

申请号：US11035369

申请日：2005-01-13

申请人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

发明人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

IPC分类号： H01L29/94

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：US20080038905A1

公开(公告)日：2008-02-14

申请号：US11875524

申请日：2007-10-19

申请人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

发明人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

IPC分类号： H01L21/20 ,  C22C16/00

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US20070090471A1

公开(公告)日：2007-04-26

申请号：US11259644

申请日：2005-10-26

申请人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

发明人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US20060166474A1

公开(公告)日：2006-07-27

申请号：US11050790

申请日：2005-01-27

申请人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

发明人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/20

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20060275977A1

公开(公告)日：2006-12-07

申请号：US11500254

申请日：2006-08-07

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

公开(公告)号：US20050269635A1

公开(公告)日：2005-12-08

申请号：US10957342

申请日：2004-10-01

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的源极和漏极扩散区域的半导体衬底，源极和漏极扩散区域被器件沟道分离; 以及位于器件沟道顶部的栅极堆叠，栅极堆叠包括高k栅极电介质，绝缘中间层和完全硅化金属栅极导体，位于高k栅极电介质和完全硅化金属之间的绝缘中间层 栅极导体，其中所述绝缘中间层能够将所述半导体结构的阈值电压和平带电压稳定到目标值。

公开(公告)号：US20060102968A1

公开(公告)日：2006-05-18

申请号：US10988733

申请日：2004-11-15

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

摘要翻译： 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：US08618511B2

公开(公告)日：2013-12-31

申请号：US12212874

申请日：2008-09-18

申请人： Josef K. Röper ,  Werner Finke ,  Martin Frank ,  Günter Schmidt ,  Siegfried Dick ,  Peter Stubenbord

发明人： Josef K. Röper ,  Werner Finke ,  Martin Frank ,  Günter Schmidt ,  Siegfried Dick ,  Peter Stubenbord

IPC分类号： G01N21/00

CPC分类号： G21K5/00 ,  G01N33/48764 ,  G01N35/00029 ,  G01N35/00732 ,  G01N2035/00108 ,  G01N2035/00168

摘要： The test elements are provided that are adapted to detect at least one analyte in a sample. At least some of the test elements are provided with a defect marking which contains information about defectiveness of the test elements. The test elements include at least one radiation-sensitive material. The test elements are exposed to at least one radiation, the radiation being adapted to induce marking in the form of at least one optically detectable change in the radiation-sensitive material.

摘要翻译： 提供了适于检测样品中的至少一种分析物的测试元件。 至少一些测试元件被提供有缺陷标记，该缺陷标记包含关于测试元件的缺陷的信息。 测试元件包括至少一种辐射敏感材料。 测试元件暴露于至少一个辐射，辐射适于以辐射敏感材料中的至少一个可光学检测的变化的形式诱导标记。

公开(公告)号：US07510682B2

公开(公告)日：2009-03-31

申请号：US10696360

申请日：2003-10-29

申请人： Martin Frank ,  Michael Fritz ,  Frank Deck

发明人： Martin Frank ,  Michael Fritz ,  Frank Deck

IPC分类号： G01N33/49

CPC分类号： G01N33/525

摘要： This invention relates to test element analysis system for the analytical investigation of body liquids. An evaluation instrument, pertaining to the system, comprises a storage container, where a plurality of test elements is held ready for use, a sample application position, where one test element at a time is brought into contact with the sample, a measuring device for the determination of a measurable variable characteristic for the analysis, and a transport device, by which one test element at a time is taken out of the test element storage container at the take out position and transported to the sample application position.

摘要翻译： 本发明涉及用于体液分析研究的测试元素分析系统。 一种与该系统有关的评价工具，包括容纳多个测试元件的便于使用的存储容器，一次测试元件与样品接触的样品施加位置，用于 确定分析的可测量变量特性，以及运送装置，通过该运送装置，一个测试元件一次从取出位置被取出测试元件储存容器并运送到样品施加位置。