公开(公告)号：US20080293259A1

公开(公告)日：2008-11-27

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

IPC分类号： H01L21/263

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

公开(公告)号：US08153514B2

公开(公告)日：2012-04-10

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L21/3205

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及 在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

公开(公告)号：US07115959B2

公开(公告)日：2006-10-03

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

公开(公告)号：US20080017936A1

公开(公告)日：2008-01-24

申请号：US11477707

申请日：2006-06-29

申请人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/78

摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.

摘要翻译： 提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。 公开了nFET和/或pFET结构。 根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在 电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

公开(公告)号：US07078300B2

公开(公告)日：2006-07-18

申请号：US10672631

申请日：2003-09-27

申请人： Evgeni Gousev ,  Huiling Shang ,  Christopher P. D'Emic ,  Paul M. Kozlowski

发明人： Evgeni Gousev ,  Huiling Shang ,  Christopher P. D'Emic ,  Paul M. Kozlowski

IPC分类号： H01L21/336

CPC分类号： H01L21/28202 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28255 ,  H01L21/3143 ,  H01L21/31658 ,  H01L21/318 ,  H01L29/518 ,  Y10S438/906 ,  Y10S438/933

摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.

摘要翻译： 公开了用作栅极电介质的Ge基材料上产生6nm以下等效氧化物厚度薄的锗氮氧化物层的方法。 该方法涉及两步法。 首先，在Ge基材料的表层中加入氮。 其次，氮掺入之后是氧化步骤。 该方法为基于Ge的场效应器件（例如MOS晶体管）的高质量栅极电介质产生优异的厚度控制。 还公开了具有薄氮氧化锗栅电介质的器件的结构和用这种器件制造的处理器。

公开(公告)号：US06642156B2

公开(公告)日：2003-11-04

申请号：US09919970

申请日：2001-08-01

申请人： Evgeni Gousev ,  Atul C. Ajmera ,  Christopher P. D'Emic

发明人： Evgeni Gousev ,  Atul C. Ajmera ,  Christopher P. D'Emic

IPC分类号： H01L21469

CPC分类号： H01L21/02326 ,  H01L21/0214 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3143 ,  H01L21/3144 ,  H01L29/518

摘要： A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

摘要翻译： 公开了一种用于形成用于集成电路器件的超薄栅极电介质的方法。 在本发明的一个示例性实施例中，该方法包括通过在氨（NH 3）气体存在下快速加热衬底，然后通过快速加热初始氮化物来再次氧化初始氮化物层，在衬底上形成初始氮化物层 在一氧化氮（NO）气体的存在下形成氮氧化物层。 氧氮化物层的氮浓度为约1.0×10 15原子/ cm 2至约6.0×10 15原子/ cm 2，并且其厚度可控制在亚范围内 。

公开(公告)号：US06444592B1

公开(公告)日：2002-09-03

申请号：US09597765

申请日：2000-06-20

申请人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Matthew W. Copel ,  Christopher P. D'Emic ,  Evgeni P. Gousev ,  Fenton Read McFeely ,  Joseph S. Newbury ,  Harald F. Okorn-Schmidt ,  Patrick R. Varekamp ,  Theodore H. Zabel

发明人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Matthew W. Copel ,  Christopher P. D'Emic ,  Evgeni P. Gousev ,  Fenton Read McFeely ,  Joseph S. Newbury ,  Harald F. Okorn-Schmidt ,  Patrick R. Varekamp ,  Theodore H. Zabel

IPC分类号： H01L21469

CPC分类号： H01L21/31691 ,  H01L28/56

摘要： A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

摘要翻译： 提供了一种将高k材料集成到CMOS处理方案中的方法。 该方法包括在半导体衬底的器件区域上形成界面氧化物，氧氮化物和/或氮化物层，所述界面层的厚度小于10埃; 和（b）在所述界面氧化物，氧氮化物和/或氮化物层上形成高k电介质材料，所述高k电介质的介电常数k大于8。

公开(公告)号：US06893979B2

公开(公告)日：2005-05-17

申请号：US09809663

申请日：2001-03-15

申请人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

发明人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L29/518 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3144

摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

摘要翻译： 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

公开(公告)号：US07109559B2

公开(公告)日：2006-09-19

申请号：US10982999

申请日：2004-11-05

申请人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

发明人： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/518 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3144

摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

摘要翻译： 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

公开(公告)号：US20130049199A1

公开(公告)日：2013-02-28

申请号：US13222469

申请日：2011-08-31

申请人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

发明人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

IPC分类号： H01L23/532 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L29/00 ,  H01L29/665 ,  H01L29/7833

摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

摘要翻译： 具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。 例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。 然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。