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    Multiple Independent On-chip Interconnect
    3.
    发明申请
    Multiple Independent On-chip Interconnect 有权

    公开(公告)号：US20220334997A1

    公开(公告)日：2022-10-20

    申请号：US17337805

    申请日：2021-06-03

    Applicant: Apple Inc.

    Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg

    IPC: G06F13/40 ,  G06F15/173

    Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

    Scalable Cache Coherency Protocol
    4.
    发明申请
    Scalable Cache Coherency Protocol 有权

    公开(公告)号：US20220083472A1

    公开(公告)日：2022-03-17

    申请号：US17315725

    申请日：2021-05-10

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

    IPC: G06F12/0815

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Hashing with Soft Memory Folding
    10.
    发明申请
    Hashing with Soft Memory Folding 有权

    公开(公告)号：US20220342806A1

    公开(公告)日：2022-10-27

    申请号：US17519284

    申请日：2021-11-04

    Applicant: Apple Inc.

    Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

    IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045

    Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

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