公开(公告)号：US20200027782A1

公开(公告)日：2020-01-23

申请号：US16037985

申请日：2018-07-17

Applicant: Applied Materials, Inc.

Inventor： Hao JIANG ,  He REN ,  Hao CHEN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

公开(公告)号：US20160307768A1

公开(公告)日：2016-10-20

申请号：US15194456

申请日：2016-06-27

Applicant: Applied Materials, Inc.

Inventor： Hao CHEN ,  Chentsau (Chris) Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/3065 ,  C23C16/50 ,  H01L21/3213 ,  H01L21/67 ,  C23C16/04 ,  C23C16/455 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/3086 ,  C23C16/04 ,  C23C16/34 ,  C23C16/345 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J37/32082 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/67742

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

Abstract translation: 多周期间隔物的第一部分形成在衬底上的图案化特征的侧壁上。 使用第一等离子体工艺在第一部分上沉积间隔层。 使用第二等离子体工艺蚀刻间隔层以在第一部分上形成多循环间隔物的第二部分。 连续重复包括沉积和蚀刻间隔层的循环，直到形成多循环间隔物。

公开(公告)号：US20200161181A1

公开(公告)日：2020-05-21

申请号：US16669082

申请日：2019-10-30

Applicant: Applied Materials, Inc.

Inventor： Wenhui WANG ,  Huixiong DAI ,  Christopher S. NGAI ,  Liqi WU ,  Wenyu ZHANG ,  Yongmei CHEN ,  Hao CHEN ,  Keith Tatseun WONG ,  Ke CHANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/033 ,  H01L21/02

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.

公开(公告)号：US20160351799A1

公开(公告)日：2016-12-01

申请号：US14755964

申请日：2015-06-30

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Mahendra PAKALA ,  Hao CHEN ,  Jaesoo AHN

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12

Abstract: Device structures and methods for fabricating device structures are provided herein. Magnetic random access memory (MRAM) devices described herein may include a film stack comprising a magnetic tunneling junction layer, a dielectric capping layer, an etch stop layer, a conductive hard mask layer, a dielectric hard mask layer, a spin on carbon layer, and an anti-reflective coating layer. The film stack may be etched by one or more selected chemistries to achieve improved film stack sidewall verticality. Memory cells having increasingly uniform and reduced critical dimensions may be fabricated utilizing the methods and devices described herein.

Abstract translation: 本文提供了用于制造器件结构的器件结构和方法。 本文描述的磁性随机存取存储器（MRAM）器件可以包括膜堆叠，其包括磁性隧道结层，介电覆盖层，蚀刻停止层，导电硬掩模层，电介质硬掩模层，自旋碳层， 和抗反射涂层。 可以通过一个或多个选择的化学物质来蚀刻膜堆叠，以实现改进的膜叠层侧壁垂直度。 可以使用本文所述的方法和装置来制造具有越来越均匀和降低的临界尺寸的存储器单元。

公开(公告)号：US20210233765A1

公开(公告)日：2021-07-29

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi YOSHIDA ,  He REN ,  Hao JIANG ,  Chenfei SHEN ,  Chi-Chou LIN ,  Hao CHEN ,  Xuesong LU ,  Mehul B. NAIK

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/66 ,  B08B5/02

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.