Silicon-containing layer for bit line resistance reduction

    公开(公告)号:US11626410B2

    公开(公告)日:2023-04-11

    申请号:US17861412

    申请日:2022-07-11

    IPC分类号: H01L27/108

    摘要: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

    Paste method to reduce defects in dielectric sputtering

    公开(公告)号:US11459651B2

    公开(公告)日:2022-10-04

    申请号:US15426102

    申请日:2017-02-07

    摘要: Embodiments of a tantalum (Ta) target pasting process for deposition chambers using RF powered processes include pasting at least a portion of the inner surfaces of the process chamber with Ta after using RF sputtering to deposit dielectric material on a wafer. Pressure levels within the process chamber are adjusted to maximize coverage of the Ta pasting layer. The Ta pasting encapsulates the dielectric material that has been inadvertently sputtered on the process chamber inner surfaces such as the shield. Oxygen is then flowed into the process chamber to form a tantalum oxide layer on the Ta pasting layer to further reduce contamination and particle generation.

    Methods for thin film material deposition using reactive plasma-free physical vapor deposition

    公开(公告)号:US10665426B2

    公开(公告)日:2020-05-26

    申请号:US14986168

    申请日:2015-12-31

    IPC分类号: H01J37/32 C23C14/00 H01J37/34

    摘要: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

    Magnetic tunnel junctions suitable for high temperature thermal processing

    公开(公告)号:US10255935B2

    公开(公告)日:2019-04-09

    申请号:US15862301

    申请日:2018-01-04

    摘要: Embodiments herein provide film stacks utilized to form a magnetic tunnel junction (MTJ) structure on a substrate, comprising: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer, wherein the capping layer comprises one or more layers; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru.

    PROCESS KIT FOR MULTI-CATHODE PROCESSING CHAMBER

    公开(公告)号:US20180350572A1

    公开(公告)日:2018-12-06

    申请号:US15614595

    申请日:2017-06-05

    IPC分类号: H01J37/34 C23C14/34 H01J37/32

    摘要: Embodiments of a process kit for use in a multi-cathode process chamber are disclosed herein. In some embodiments, a process kit includes a rotatable shield having a base, a conical portion extend downward and radially outward from the base, and a collar portion extending radially outward from a bottom of the conical portion; an inner deposition ring having a leg portion, a flat portion extending radially inward from the leg portion, a first recessed portion extending radially inward from the flat portion, and a first lip extending upward from an innermost section of the first recessed portion; and an outer deposition ring having a collar portion, an upper flat portion disposed above and extending radially inward from the collar portion, a second recessed portion extending inward from the upper flat portion, and a second lip extending upward from an innermost section of the second recessed portion.