公开(公告)号：US20200098574A1

公开(公告)日：2020-03-26

申请号：US16696229

申请日：2019-11-26

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun WONG ,  Thomas Jongwan KWON ,  Sean KANG ,  Ellie Y. YIEH

IPC: H01L21/285 ,  H01L27/115 ,  H01L21/768 ,  C23C16/56 ,  C23C16/08 ,  C23C16/14

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

公开(公告)号：US20160293437A1

公开(公告)日：2016-10-06

申请号：US14968500

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。

公开(公告)号：US20150140827A1

公开(公告)日：2015-05-21

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling KAO ,  Sean KANG ,  Jeremiah T. PENDER ,  Srinivas D. NEMANI ,  He REN ,  Mehul NAIK

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。

公开(公告)号：US20230223268A1

公开(公告)日：2023-07-13

申请号：US17572397

申请日：2022-01-10

Applicant: Applied Materials, Inc.

Inventor： Sean KANG ,  Olivier LUERE ,  Kenji TAKESHITA ,  Sanghyuk CHOI ,  Mengnan ZOU ,  Zihao DING

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/02126 ,  H01L21/31116

Abstract: Embodiments of the present disclosure generally relate to a method for etching a film stack with high selectivity and low etch recipe transition periods. In one embodiment, a method for etching a film stack having stacked pairs of oxide and nitride layers is described. The method includes transferring a substrate having a film stack formed thereon into a processing chamber, providing a first bias voltage to the substrate, etching an oxide layer of the film stack while providing the first bias voltage to the substrate, providing a second bias voltage to the substrate, the second bias voltage greater than the first bias voltage, and etching a nitride layer of the film stack while providing the second bias voltage to the substrate.

公开(公告)号：US20160293438A1

公开(公告)日：2016-10-06

申请号：US15080117

申请日：2016-03-24

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

公开(公告)号：US20160133480A1

公开(公告)日：2016-05-12

申请号：US14535055

申请日：2014-11-06

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungmin KO ,  Sean KANG

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76897

Abstract: In some embodiments methods of processing a substrate include: providing a substrate having a contact structure formed on the substrate, wherein the contact structure comprises a feature defined by gate structures, a silicon nitride layer disposed on a upper surface of the gate structures and on sidewalls and a bottom of the feature, and an oxide layer disposed over the silicon nitride layer and filling the feature; etching an opening through the oxide layer to the silicon nitride layer disposed on the bottom of the opening, wherein a width of the opening is less than a width of the feature; expanding the opening in the oxide layer to form a tapered profile; exposing the substrate to ammonia and nitrogen trifluoride to form an ammonium fluoride gas that forms an ammonium hexafluorosilicate film on the oxide layer; and heating the substrate to a second temperature to sublimate the ammonium hexafluorosilicate film.

Abstract translation: 在一些实施例中，处理衬底的方法包括：提供具有形成在衬底上的接触结构的衬底，其中接触结构包括由栅极结构限定的特征，设置在栅极结构的上表面上和侧壁上的氮化硅层 和该特征的底部，以及设置在氮化硅层上并填充该特征的氧化物层; 将通过所述氧化物层的开口蚀刻到设置在所述开口底部的所述氮化硅层，其中所述开口的宽度小于所述特征的宽度; 膨胀氧化层中的开口以形成锥形轮廓; 将基板暴露于氨和三氟化氮以形成在氧化物层上形成六氟硅酸铵膜的氟化铵气体; 并将衬底加热至第二温度以使六氟硅酸铵膜升华。

公开(公告)号：US20230298893A1

公开(公告)日：2023-09-21

申请号：US18202838

申请日：2023-05-26

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun WONG ,  Thomas Jongwan KWON ,  Sean KANG ,  Ellie Y. YIEH

IPC: H01L21/285 ,  C23C16/14 ,  H10B69/00 ,  C23C16/08 ,  C23C16/56 ,  H01L21/768

CPC classification number: H01L21/28556 ,  C23C16/14 ,  H10B69/00 ,  C23C16/08 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/76883 ,  H10B41/20

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

公开(公告)号：US20220336222A1

公开(公告)日：2022-10-20

申请号：US17244873

申请日：2021-04-29

Applicant: Applied Materials, Inc.

Inventor： Hailong ZHOU ,  Sean KANG ,  Kenji TAKESHITA ,  Rajinder DHINDSA ,  Taehwan LEE ,  Iljo KWAK

IPC: H01L21/311

Abstract: Embodiments of this disclosure include a method of processing a substrate that includes etching a first dielectric material formed on a substrate that is disposed on a substrate supporting surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process may include delivering a process gas to the processing region, wherein the process gas comprises a first fluorocarbon containing gas and a first process gas, delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode to form a plasma in the processing region, and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode disposed within the substrate support assembly. The first pulsed voltage waveform comprises a series of repeating pulsed waveform cycles that each include a first portion that occurs during a first time interval, a second portion that occurs during a second time interval, and a peak-to-peak voltage. The pulsed voltage waveform is substantially constant during at least a portion of the second time interval.

公开(公告)号：US20170358490A1

公开(公告)日：2017-12-14

申请号：US15332737

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sean KANG ,  Keith Tatseun WONG ,  He REN ,  Mehul B. NAIK ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/768

CPC classification number: H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53257

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US20150214101A1

公开(公告)日：2015-07-30

申请号：US14540577

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Chia-Ling KAO ,  Sean KANG ,  Jeremiah T P PENDER ,  Srinivas D. NEMANI ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract translation: 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。