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    Low cost cryptographic accelerator
    1.
    发明授权
    Low cost cryptographic accelerator 有权

    公开(公告)号：US11841981B2

    公开(公告)日：2023-12-12

    申请号：US16948480

    申请日：2020-09-21

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen ,  Martin Olsson ,  Arne Aas

    IPC: H04L9/06 ,  G06F21/72

    CPC classification number: G06F21/72 ,  H04L9/06 ,  H04L9/0631 ,  H04L9/0643 ,  H04L2209/12

    Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.

    Low Cost Cryptographic Accelerator
    3.
    发明申请
    Low Cost Cryptographic Accelerator 审中-公开

    公开(公告)号：US20180089467A1

    公开(公告)日：2018-03-29

    申请号：US15679134

    申请日：2017-08-16

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen ,  Martin Olsson ,  Arne Aas

    IPC: G06F21/72 ,  H04L9/06

    Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.

    Managing wait states for memory access
    4.
    发明授权
    Managing wait states for memory access 有权

    公开(公告)号：US09710169B2

    公开(公告)日：2017-07-18

    申请号：US15223227

    申请日：2016-07-29

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

    Inter-process signaling system and method
    5.
    发明授权
    Inter-process signaling system and method 有权

    公开(公告)号：US10713188B2

    公开(公告)日：2020-07-14

    申请号：US15277971

    申请日：2016-09-27

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen

    IPC: G06F13/24 ,  G06F13/16 ,  G06F9/52 ,  G06F15/173

    Abstract: An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

    MANAGING WAIT STATES FOR MEMORY ACCESS
    7.
    发明申请
    MANAGING WAIT STATES FOR MEMORY ACCESS 有权
    管理用于存储器访问的等待状态

    公开(公告)号：US20160335000A1

    公开(公告)日：2016-11-17

    申请号：US15223227

    申请日：2016-07-29

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

    Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

    Processor maintaining reset-state after reset signal is suspended
    8.
    发明授权
    Processor maintaining reset-state after reset signal is suspended 有权
    复位信号暂停后处理器保持复位状态

    公开(公告)号：US09423843B2

    公开(公告)日：2016-08-23

    申请号：US13624651

    申请日：2012-09-21

    Applicant: Atmel Corporation

    Inventor： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

    IPC: G06F1/24 ,  G06F11/267

    CPC classification number: G06F1/24 ,  G06F11/267

    Abstract: Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

    Abstract translation: 描述了处理器复位保持控制的系统和技术。 所描述的系统包括控制器，用于基于外部复位信号和外部调试信号检测保持请求，并且基于对保持信号的检测产生保持信号，其中保持信号在外部复位信号中断之后继续 ; 响应于外部复位信号的系统组件; 响应于所述保持信号的处理器，其中所述保持信号使所述处理器进入复位状态，并且在所述外部复位信号已经中断之后保持所述复位状态; 以及被配置为在处理器处于复位状态时允许对系统组件的外部访问的系统管理器。 控制器可以被配置为响应于明确的请求中断保持信号。

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