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1.发明申请Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor 审中-公开用于确定在处理器中保持活动的执行单元数量的装置和方法公开(公告)号：US20150241954A1
公开(公告)日：2015-08-27
申请号：US14697553
申请日：2015-04-27
申请人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.
摘要翻译： 描述了在处理器核心中包括多个执行单元的处理器。 处理器还可以包括功率管理电路，以从多个配置中确定具有最低功率成本的配置，每个配置对于相同的主动性能状态具有不同数量的启用的执行单元。 一种方法可以包括：通过处理器的功率管理电路确定来自多个配置的具有最低功率成本的配置，每个配置在处理器的处理器核心中具有不同数量的启用的执行单元，用于相同的主动性能状态。
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2.发明申请Apparatus and Method For Determining the Number of Execution Cores To Keep Active In A Processor 有权用于确定在处理器中保持活动的执行核心数量的装置和方法公开(公告)号：US20140095904A1
公开(公告)日：2014-04-03
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译： 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。
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3.发明授权Apparatus and method for determining the number of execution cores to keep active in a processor 有权用于确定在处理器中保持活动的执行核心数量的装置和方法公开(公告)号：US09037889B2
公开(公告)日：2015-05-19
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译： 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。
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公开(公告)号：US20140068293A1
公开(公告)日：2014-03-06
申请号：US13783978
申请日：2013-03-04
申请人： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
发明人： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
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公开(公告)号：US20150095620A1
公开(公告)日：2015-04-02
申请号：US14039151
申请日：2013-09-27
IPC分类号： G06F9/30
CPC分类号： G06F9/30083 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/4893 , G06F11/3466 , G06F12/084 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括第一逻辑，用于至少部分地基于所述域的活动状态驻留，停止持续时间和存储器带宽来计算处理器域的可扩展性值，并且确定用于 该域至少部分地基于域的当前操作频率和可扩展性值。 描述和要求保护其他实施例。
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公开(公告)号：US20210064426A1
公开(公告)日：2021-03-04
申请号：US16554940
申请日：2019-08-29
IPC分类号： G06F9/48 , G06F1/3206 , G06F9/50 , G06F1/08 , G06F1/10
摘要： In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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公开(公告)号：US20150095666A1
公开(公告)日：2015-04-02
申请号：US14039193
申请日：2013-09-27
IPC分类号： G06F1/26
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/26 , G06F1/3203 , G06F1/3212 , G06F1/324 , G06F11/3024 , G06F11/3058 , Y02D10/126 , Y02D10/174
摘要： In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心和耦合到核心的功率控制器。 功率控制器可以包括功率包络控制逻辑以接收多个功率包络参数，并且使得处理器的功率消耗水平能够超过时间窗口的一部分的功率突发阈值。 该部分可以根据时间窗口的长度和占空比来确定，其中功率包络参数被编程用于包括处理器的系统，并且包括功率脉冲串阈值，时间窗口和占空比。 描述和要求保护其他实施例。
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公开(公告)号：US20130179706A1
公开(公告)日：2013-07-11
申请号：US13782473
申请日：2013-03-01
申请人： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
发明人： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
摘要： In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。
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9.发明授权Mechanism to provide workload and configuration-aware deterministic performance for microprocessors 有权为微处理器提供工作负载和配置感知确定性性能的机制公开(公告)号：US09037840B2
公开(公告)日：2015-05-19
申请号：US13538546
申请日：2012-06-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC分类号： G06F15/177 , G06F1/00 , G06F1/32 , G06F1/20
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.
摘要翻译： 描述了包括具有处理器和裸片上非易失性存储资源的半导体芯片的装置。 在线非易失性存储器是为处理器的相同性能状态存储用于处理器的不同配置和/或使用情况的不同的适当的性能相关信息。
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10.发明申请MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS 有权为微处理器提供工作负载和配置 - 确定性能的机制公开(公告)号：US20140006761A1
公开(公告)日：2014-01-02
申请号：US13538546
申请日：2012-06-29
申请人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
发明人： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.
摘要翻译： 描述了包括具有处理器和裸片上非易失性存储资源的半导体芯片的装置。 在线非易失性存储器是为处理器的相同性能状态存储用于处理器的不同配置和/或使用情况的不同的适当的性能相关信息。
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