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19 条记录 (耗时 0.021 秒)

    SRAM cell with capacitor
    2.
    发明授权
    SRAM cell with capacitor 失效
    带电容器的SRAM单元

    公开(公告)号：US5541427A

    公开(公告)日：1996-07-30

    申请号：US162588

    申请日：1993-12-03

    申请人： Barbara A. Chappell ,  Bijan Davari ,  George A. Sai-Halasz ,  Yuan Taur

    发明人： Barbara A. Chappell ,  Bijan Davari ,  George A. Sai-Halasz ,  Yuan Taur

    IPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/108

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.

    摘要翻译： 存储锁存器，包括在所述衬底上的栅极绝缘层，穿过所述绝缘层形成的浅沟槽和所述衬底中的沟槽以提供器件绝缘; 以及在浅沟槽之间的衬底中的掺杂区域。 掺杂区域定义源和漏极。 栅极堆叠形成在与掺杂区域相邻的氧化物区域上。 在栅极堆叠之间形成平坦化的绝缘体。 在平坦化的绝缘体中提供了开口，用于与掺杂区域和栅极叠层的接触。 导电材料填充开口以形成用于掺杂区域和栅极叠层的触点。 平坦化绝缘体上的图案化的导电材料层连接用于闩锁的布线部分的所述触点中的所选择的一个。 六器件SRAM单元包括形成在衬底中的深隔离沟槽; 第一锁存器，包括在所述沟槽的第一侧上由p型材料形成的两个晶体管; 包括在与沟槽的第一侧相对的沟槽的第二侧上由n型材料形成的两个晶体管的第二锁存器以及用于将第一锁存器的晶体管与第二锁存器的晶体管电交叉布线的连接装置。 在形成锁存器时，使用用于单独形成与半导体衬底上的扩散区域和栅极堆叠的接触的自对准工艺。

    Buried capacitor for silicon-on-insulator structure
    3.
    发明授权
    Buried capacitor for silicon-on-insulator structure 失效
    埋入式电容器，用于绝缘体上硅结构

    公开(公告)号：US06188122B1

    公开(公告)日：2001-02-13

    申请号：US09231615

    申请日：1999-01-14

    申请人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    发明人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    IPC分类号： H01L2701

    CPC分类号： H01L29/66181 ,  H01L27/1203

    摘要： A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

    摘要翻译： 一种用于制造绝缘体上硅（SOI）结构的电容器的工艺。 SOI结构具有在p型硅基底层的一部分内形成的p型硅基底层，埋入氧化物层，硅层和n +层。 该工艺包括以下步骤：在p型硅基层中形成掩埋氧化物层和硅层，在p型硅基层的一部分中形成n +层，并形成p型硅基层的导电路径 硅基层和n +层延伸穿过掩埋的氧化物和硅层。

    Non-destructive testing of semiconductors using acoustic wave method
    5.
    发明授权
    Non-destructive testing of semiconductors using acoustic wave method 失效
    使用声波法对半导体的非破坏性测试

    公开(公告)号：US4621233A

    公开(公告)日：1986-11-04

    申请号：US570496

    申请日：1984-01-13

    申请人： Bijan Davari ,  Pankaj Das

    发明人： Bijan Davari ,  Pankaj Das

    IPC分类号： G01R31/265 ,  G01R31/32 ,  G01R29/22

    CPC分类号： G01R31/265

    摘要： A contactless non-destructive technique for measuring at least one surface property of a first semiconductor material surface utilizes an electrically conductive interdigital transducer and a metal plate defined on a piezoelectric material. The metal plate has a window therein and the semiconductor material is positioned with its first surface over the window and facing the exposed piezoelectric material of the window. A radio frequency pulse is applied to the interdigital transducer to generate a surface acoustic wave on the piezoelectric material. This produces a transverse electric field which extends above the surface of the piezoelectric material and propagates across the window. This field acts as a probing field in the semiconductor material at the surface facing the piezoelectric material, and due to acousto-electric interaction a transverse acousto-electric voltage is produced. A dc voltage is applied to an opposite surface of the semiconductor to change the surface potential of the semiconductor material. A characteristic curve plotting the transverse acoustoelectric voltage against the dc voltage can be utilized to determine various surface properties for the semiconductor material. The window also defines the position where this surface property is measured.

    摘要翻译： 用于测量第一半导体材料表面的至少一个表面性质的非接触非破坏性技术利用限定在压电材料上的导电叉指式换能器和金属板。 金属板在其中具有窗口，并且半导体材料被定位成其第一表面位于窗口上并且面向窗口的暴露的压电材料。 射频脉冲施加到叉指式换能器以在压电材料上产生表面声波。 这产生横向电场，该横向电场在压电材料的表面上方延伸并且在窗口上传播。 该场作为面向压电材料的表面的半导体材料中的探测场，并且由于声电相互作用，产生横向声电压。 将直流电压施加到半导体的相对表面以改变半导体材料的表面电位。 可以利用绘制横向声电压与直流电压的特性曲线来确定半导体材料的各种表面性质。 窗口还定义了测量该表面性质的位置。

    Methods and apparatus for optimizing combined cycle/combined process facilities
    6.
    发明申请
    Methods and apparatus for optimizing combined cycle/combined process facilities 失效
    优化联合循环/组合加工设备的方法和设备

    公开(公告)号：US20060178782A1

    公开(公告)日：2006-08-10

    申请号：US11055312

    申请日：2005-02-10

    申请人： Peter Pechtl ,  Martin Posch ,  Bijan Davari ,  Marco Dieleman

    发明人： Peter Pechtl ,  Martin Posch ,  Bijan Davari ,  Marco Dieleman

    IPC分类号： G05B17/00 ,  G06F17/50

    CPC分类号： G05B19/41885 ,  G05B13/024 ,  Y02E20/14 ,  Y02E20/16 ,  Y02P80/154 ,  Y02P90/26

    摘要： Methods and systems for operating combined cycle electrical generating plants is provided. The method includes simulating the electrical power plant performance, simulating the steam utilizing process plant performance, parameterizing plant equipment and plant performance using the power plant and process plant simulation results, and solving parameterized simultaneous equations and constraints with an objective function to determine parameter settings that facilitate enhancing an efficiency of the combined cycle electrical generating/steam-utilizing process plant.

    摘要翻译： 提供了操作联合循环发电厂的方法和系统。 该方法包括模拟电厂性能，模拟使用过程工厂性能的蒸汽，使用发电厂参数化设备设备和设备性能，以及过程工厂模拟结果，并用目标函数求解参数化的联立方程和约束，以确定参数设置 有助于提高联合循环发电/蒸汽利用过程工厂的效率。

    Silicon-on-insulator vertical array device trench capacitor DRAM
    7.
    发明授权
    Silicon-on-insulator vertical array device trench capacitor DRAM 有权
    绝缘体上的垂直阵列器件沟槽电容器DRAM

    公开(公告)号：US06566177B1

    公开(公告)日：2003-05-20

    申请号：US09427257

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L2100

    CPC分类号： H01L27/10864 ,  H01L27/1087

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

    摘要翻译： 一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。 存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。 掩埋氧化层将SOI层与硅衬底隔离。 沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。 最初，在晶圆中形成掩埋氧化物层。 深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。 在沟槽中形成保护侧壁。 然后，将深沟槽蚀刻到衬底中。 衬底中的体积被扩大以形成瓶形沟槽。 在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。 在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。 浅沟槽隔离（STI）用于隔离和定义细胞。 在晶片上形成位线和字线。

    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
    8.
    发明授权
    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap 失效
    绝缘体上的垂直阵列DRAM单元，具有自对准埋地带

    公开(公告)号：US06426252B1

    公开(公告)日：2002-07-30

    申请号：US09427256

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

    摘要翻译： 绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。 存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。 形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。 深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。 每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 在SOI层的BOX层中形成凹部。 凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。 将掺杂剂注入到晶片中以限定器件区域。 存取晶体管栅极沿SOI层侧壁形成。 形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。 形成字词和位线以完成内存数组。

    Patterned SOI regions on semiconductor chips
    10.
    发明授权
    Patterned SOI regions on semiconductor chips 有权
    半导体芯片上的图案化SOI区域

    公开(公告)号：US06756257B2

    公开(公告)日：2004-06-29

    申请号：US09975435

    申请日：2001-10-11

    申请人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

    发明人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

    摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

    摘要翻译： 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。