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    Security apparatus for motor vehicles
    1.
    发明申请
    Security apparatus for motor vehicles 审中-公开
    机动车安全装置

    公开(公告)号：US20060170536A1

    公开(公告)日：2006-08-03

    申请号：US11116467

    申请日：2005-04-28

    Applicant: Cheng-Hung Yu ,  Cheng-Peng Liu

    Inventor： Cheng-Hung Yu ,  Cheng-Peng Liu

    IPC: B60R25/10 ,  G08B3/10 ,  G08B23/00

    CPC classification number: G10K9/22

    Abstract: A security apparatus for motor vehicles is disclosed, and is featured in integrating all the components into one body as an all-in-one form and in filling resin into the housing of the security apparatus so as to completely cover an electric circuit unit and the interior surface of a siren. The present invention is alternately featured in providing a metal cover covering the externally-exposed surface of the siren for protecting the siren; providing fastening elements each of which has a head hole of special pattern, thereby preventing the security apparatus from being unlawfully dismantled; and providing several detecting modes and power-saving modes, so as to effectively and reliably provide the antitheft function for motor vehicles.

    Abstract translation: 公开了一种用于机动车辆的安全装置，其特征在于将所有部件作为一体式形成一体，并将树脂填充到安全装置的壳体中，以完全覆盖电路单元，并且 警笛的内表面。 本发明的另一特征在于提供一种覆盖警报器的外部暴露表面的金属盖，用于保护警报; 提供每个具有特殊图案的头孔的紧固元件，从而防止安全装置被非法拆除; 并提供多种检测模式和省电模式，有效可靠地为汽车提供防盗功能。

    Color filter array having hybrid color filters and manufacturing method thereof
    2.
    发明授权
    Color filter array having hybrid color filters and manufacturing method thereof 有权
    具有混合滤色器的滤色器阵列及其制造方法

    公开(公告)号：US08765333B2

    公开(公告)日：2014-07-01

    申请号：US13561103

    申请日：2012-07-30

    Applicant: Cheng-Hung Yu

    Inventor： Cheng-Hung Yu

    IPC: G02B5/20 ,  G03F7/20

    CPC classification number: G02B5/201 ,  G03F7/0007

    Abstract: A method for manufacturing a color filter array having hybrid color filters includes providing a high-grade photoresist and a low-grade photoresist, forming a plurality of first color filters on a substrate, and forming a plurality of second color filters and a plurality of third color filters on the substrate. The first color filters include the high-grade photoresist, and the second color filters and the third color filters include the low-grade photoresist. The high-grade photoresist of the first color filters includes a first amount of large size pigments in one unit area and the low-grade photoresists of the second color filters and the third color filters include a second amount of large size pigments in one unit area. A ratio of the second amount to the first amount is equal to or larger than 1.

    Abstract translation: 一种制造具有混合滤色器的滤色器阵列的方法，包括提供高级光致抗蚀剂和低等级光致抗蚀剂，在衬底上形成多个第一滤色器，以及形成多个第二滤色器和多个第三滤色器 基底上的滤色器。 第一滤色器包括高级光致抗蚀剂，第二滤色器和第三滤色器包括低等级光致抗蚀剂。 第一滤色器的高级光致抗蚀剂包括在一个单位面积中的第一量的大尺寸颜料和第二滤色器的低等级光致抗蚀剂和第三滤色器在一个单位面积中包括第二量的大尺寸颜料 。 第二量与第一量的比例等于或大于1。

    MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE
    3.
    发明申请
    MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE 审中-公开
    多层三维电路结构

    公开(公告)号：US20110253435A1

    公开(公告)日：2011-10-20

    申请号：US13166133

    申请日：2011-06-22

    Applicant: Han-Pei Huang ,  Cheng-Hung Yu

    Inventor： Han-Pei Huang ,  Cheng-Hung Yu

    IPC: H05K1/03 ,  H05K1/11

    CPC classification number: H05K3/4644 ,  B33Y10/00 ,  B33Y80/00 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/06 ,  H05K3/185 ,  H05K3/205 ,  H05K3/386 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.

    Abstract translation: 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。

    METHOD OF FABRICATING IMAGE SENSOR AND REWORKING METHOD THEREOF
    4.
    发明申请
    METHOD OF FABRICATING IMAGE SENSOR AND REWORKING METHOD THEREOF 有权
    制作图像传感器的方法及其制作方法

    公开(公告)号：US20110212567A1

    公开(公告)日：2011-09-01

    申请号：US12714093

    申请日：2010-02-26

    Applicant: Hsin-Ting TSAI ,  Cheng-Hung Yu ,  Chin-Kuang Liu ,  Kun-Yen Hsu

    Inventor： Hsin-Ting TSAI ,  Cheng-Hung Yu ,  Chin-Kuang Liu ,  Kun-Yen Hsu

    IPC: H01L31/0232 ,  H01L31/18 ,  H01L27/14

    CPC classification number: H01L27/14687 ,  H01L27/14636 ,  H01L27/14685

    Abstract: A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal layer and a first planarization layer having an opening exposing the patterned metal layer in the pad region are sequentially formed on the substrate. A color filter array is formed on the first planarization layer in the pixel array region. A second planarization layer is formed to cover the color filter array and filled into the opening. A plurality of microlens is formed above the color filter array on the second planarization layer. A capping layer is conformally formed on the microlens and the second planarization layer. An etching step is performed to remove the capping layer and the second planarization layer in the opening so as to expose the patterned metal layer in the pad region.

    Abstract translation: 提供一种制造图像传感器装置的方法。 首先，提供包括像素阵列区域和衬垫区域的衬底。 图案化金属层和具有露出焊盘区域中的图案化金属层的开口的第一平坦化层依次形成在基板上。 在像素阵列区域中的第一平坦化层上形成滤色器阵列。 形成第二平坦化层以覆盖滤色器阵列并填充到开口中。 在第二平坦化层上的滤色器阵列上方形成多个微透镜。 覆盖层保形地形成在微透镜和第二平坦化层上。 执行蚀刻步骤以去除开口中的覆盖层和第二平坦化层，以暴露焊盘区域中的图案化金属层。

    Wafer for manufacturing image sensors, test key layout for defects inspection, and methods for manufacturing image sensors and for forming test key
    5.
    发明授权
    Wafer for manufacturing image sensors, test key layout for defects inspection, and methods for manufacturing image sensors and for forming test key 有权
    用于制造图像传感器的晶片，用于缺陷检查的测试键布局，以及用于制造图像传感器和形成测试键的方法

    公开(公告)号：US08003983B2

    公开(公告)日：2011-08-23

    申请号：US11379229

    申请日：2006-04-19

    Applicant: Cheng-Hung Yu

    Inventor： Cheng-Hung Yu

    IPC: H01L23/544

    CPC classification number: H01L27/14627

    Abstract: A wafer for manufacturing image sensors is disclosed. The wafer includes an image sensor and a test key. The image sensor includes a plurality of micro-lenses; the test key includes a plurality of micro-lens samples for defects inspection. The arrangement of the micro-lens samples on the test key is substantially different from the arrangement of the micro-lenses on the image sensor. The arrangement of the micro-lens samples on the test key allows defects inspection to become less complicated.

    Abstract translation: 公开了一种用于制造图像传感器的晶片。 晶片包括图像传感器和测试键。 图像传感器包括多个微透镜; 测试键包括用于缺陷检查的多个微透镜样本。 微透镜样品在测试键上的布置与图像传感器上的微透镜的布置显着不同。 微透镜样品在测试键上的布置使得缺陷检查变得不那么复杂。

    Multilayer three-dimensional circuit structure and manufacturing method thereof
    6.
    发明授权
    Multilayer three-dimensional circuit structure and manufacturing method thereof 有权
    多层三维电路结构及其制造方法

    公开(公告)号：US07987589B2

    公开(公告)日：2011-08-02

    申请号：US12333014

    申请日：2008-12-11

    Applicant: Han-Pei Huang ,  Cheng-Hung Yu

    Inventor： Han-Pei Huang ,  Cheng-Hung Yu

    IPC: H05K3/02

    CPC classification number: H05K3/4644 ,  B33Y10/00 ,  B33Y80/00 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/06 ,  H05K3/185 ,  H05K3/205 ,  H05K3/386 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.

    Abstract translation: 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。

    Reticle alignment procedure
    9.
    发明授权
    Reticle alignment procedure 有权
    标线校准程序

    公开(公告)号：US06936386B2

    公开(公告)日：2005-08-30

    申请号：US10605677

    申请日：2003-10-17

    Applicant: Cheng-Hung Yu

    Inventor： Cheng-Hung Yu

    IPC: G01B11/00 ,  G03C5/00 ,  G03F7/00 ,  G03F9/00 ,  H01L21/00 ,  H01L21/027

    CPC classification number: G03F9/7011 ,  G03F9/7019 ,  G03F9/7088

    Abstract: A semiconductor wafer has at least one pre-layer on-wafer alignment mark (pre-layer on-wafer AM) on a top surface of the semiconductor wafer. A baseline check (BCHK) is performed to align a current-layer reticle AM on a current-layer reticle with the pre-layer on-wafer AM. By capturing and comparing signals of the current-layer reticle AM and the pre-layer on-wafer AM, a corresponding coordinate of the current-layer reticle to the semiconductor wafer is calibrated. Finally, a lithography process is performed to transfer the layout of the current-layer reticle AM to the top surface of the semiconductor wafer to form a corresponding current-layer on-wafer AM.

    Abstract translation: 半导体晶片在半导体晶片的顶表面上具有至少一个晶片上对准标记（晶片上的预层）。 执行基线检查（BCHK）以将当前层掩模版上的当前层标线AM与晶片上的AM前层对准。 通过捕获和比较当前层标线AM和晶片AM上的晶片AM的信号，校准当前层掩模版对半导体晶片的对应坐标。 最后，进行光刻处理以将当前层标线AM的布局转移到半导体晶片的顶表面以形成相应的晶片上的电流层AM。

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