Abstract:
A method for manufacturing a color filter array having hybrid color filters includes providing a high-grade photoresist and a low-grade photoresist, forming a plurality of first color filters on a substrate, and forming a plurality of second color filters and a plurality of third color filters on the substrate. The first color filters include the high-grade photoresist, and the second color filters and the third color filters include the low-grade photoresist. The high-grade photoresist of the first color filters includes a first amount of large size pigments in one unit area and the low-grade photoresists of the second color filters and the third color filters include a second amount of large size pigments in one unit area. A ratio of the second amount to the first amount is equal to or larger than
Abstract:
An image sensor is disclosed. The image sensor includes a substrate, at least a color filter, and a microlens disposed on the color filter. The substrate includes a passivation layer thereon, and the color filter is disposed on the passivation layer, in which the color filter is truncated.
Abstract:
A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal layer and a first planarization layer having an opening exposing the patterned metal layer in the pad region are sequentially formed on the substrate. A color filter array is formed on the first planarization layer in the pixel array region. A second planarization layer is formed to cover the color filter array and filled into the opening. A plurality of microlens is formed above the color filter array on the second planarization layer. A capping layer is conformally formed on the microlens and the second planarization layer. An etching step is performed to remove the capping layer and the second planarization layer in the opening so as to expose the patterned metal layer in the pad region.
Abstract:
A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.
Abstract:
A method for fabricating an image sensor, which includes the following steps, is provided. A semiconductor substrate including a sensor array, a pad and a passivation layer is provided, and the passivation layer covers the sensor array and the pad. An opening, which comprises tapered sidewalls not perpendicular to a bared surface of the pad, is formed in the semiconductor substrate to expose the pad. An under layer is formed on the semiconductor substrate, and covers the pad and the passivation layer. A color filter array is formed on the under layer and over the corresponding sensor array. A planar layer is formed on the color filter array. A portion of the under layer is removed to expose the pad. A plurality of U-lenses is formed on the planar layer.
Abstract:
A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
Abstract:
A selective metal surface treatment process of a circuit board, which has a solder mask and a multiple of selective metal treatment surface areas, wherein the solder mask covers the surface of the circuit board but exposes the selective metal surface treatment areas, is provided. The selective metal surface treatment process includes using a printhead to selectively print a resist on a selective metal surface treatment area, performing a surface treatment of the other selective metal surface treatment areas, and removing the resist. A selective metal surface treatment apparatus used for performing the selective metal surface treatment process of the circuit board is also provided. Through the present invention, unnecessary waste of the materials in the process is reduced and the processing time is shortened.
Abstract:
An image sensor device including a substrate, a plurality of photo sensors, a dielectric layer, a planar layer, a plurality of color filters, a plurality of microlenses, and a shield layer is provided. The photo sensors are disposed in the substrate, and the dielectric layer is disposed over the photo sensors and the substrate. The planar layer is disposed over the dielectric layer. The color filters are disposed in the planar layer, wherein each of the color filters is disposed over each of the photo sensors. The microlenses are disposed over the planar layer, wherein each of the microlenses is disposed over each of the color filter. The shield layer including a plurality of openings is disposed in the planar layer and is disposed under or over the color filters, wherein each of the openings is disposed over each of the color filters.
Abstract:
A semiconductor wafer has at least one pre-layer on-wafer alignment mark (pre-layer on-wafer AM) on a top surface of the semiconductor wafer. A baseline check (BCHK) is performed to align a current-layer reticle AM on a current-layer reticle with the pre-layer on-wafer AM. By capturing and comparing signals of the current-layer reticle AM and the pre-layer on-wafer AM, a corresponding coordinate of the current-layer reticle to the semiconductor wafer is calibrated. Finally, a lithography process is performed to transfer the layout of the current-layer reticle AM to the top surface of the semiconductor wafer to form a corresponding current-layer on-wafer AM.
Abstract:
A developer cup. The developer cup includes a bed. A central spindle is vertically and rotatably coupled to a center of the bed through an end of the central spindle. A chuck is vertically coupled to an end of the central spindle opposite to the bed end. An upper coupling is coupled to the central spindle between the chuck and the bed, wherein the chuck. A lower coupling is moveably coupled to the central spindle between the upper coupling and the bed. The annular cup has an upper wheel and a lower wheel, wherein the upper wheel is aligned with the lower wheel, the upper wheel is coupled to the lower wheel through a plurality of the brackets, and the lower wheel is smaller than the upper wheel.