摘要:
Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.
摘要:
Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.
摘要:
Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W.
摘要:
Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W.
摘要:
Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.
摘要:
Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.
摘要:
A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.
摘要:
Piezoelectric deposition for BAW resonators wherein a thin amorphous layer of AlN over the bottom electrode before depositing a second layer of AlN over the amorphous layer of AlN, the depositing occurring at a temperature allowing the deposited AlN to self-organize into a desired columnar phase. The bottom electrode may have acoustic isolation thereunder, such as a Bragg mirror. Various details of the fabrication process are disclosed.
摘要:
A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.
摘要:
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.