利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

71 条记录 (耗时 0.026 秒)

    Planarization Methods
    1.
    发明申请
    Planarization Methods 有权
    平面化方法

    公开(公告)号：US20100005654A1

    公开(公告)日：2010-01-14

    申请号：US12172079

    申请日：2008-07-11

    申请人： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

    发明人： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

    IPC分类号： H05K3/02

    CPC分类号： H03H3/02 ,  H03H9/175 ,  H03H9/584 ,  H03H9/589 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    摘要： Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

    摘要翻译： 描述了在平面或平面化基板上制造诸如BAW器件和电容器之类的器件的平面表面的平面化方法。 根据该方法，沉积和图案化金属层，并且使用高密度等离子体化学气相沉积（HDP CVD）工艺将氧化物层沉积到等于金属层厚度的厚度。 HDP CVD工艺在图案化金属的图案化金属层的边缘上向上逐渐变细的氧化层。 然后，在从图案化的金属层掩蔽和蚀刻氧化物层之后，图案化的金属层和周围的氧化物层形成基本平坦的层，被图案化层的边缘处的小的剩余的氧化物突起中断。 这些小的剩余氧化物突起可能太小而不能显着地扰乱另外的氧化物或其它层的平坦度，或者可以通过施加另一HDP CVD氧化物膜进一步减轻它们。

    Planarization method in the fabrication of a circuit
    2.
    发明授权
    Planarization method in the fabrication of a circuit 有权
    电路制造中的平面化方法

    公开(公告)号：US07966722B2

    公开(公告)日：2011-06-28

    申请号：US12172079

    申请日：2008-07-11

    申请人： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

    发明人： David Hart ,  David McDonald ,  Guillaume Bouche ,  Sudarsan Uppili

    IPC分类号： H05K3/02

    CPC分类号： H03H3/02 ,  H03H9/175 ,  H03H9/584 ,  H03H9/589 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    摘要： Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

    摘要翻译： 描述了在平面或平面化基板上制造诸如BAW器件和电容器之类的器件的平面表面的平面化方法。 根据该方法，沉积和图案化金属层，并且使用高密度等离子体化学气相沉积（HDP CVD）工艺将氧化物层沉积到厚度等于金属层的厚度。 HDP CVD工艺在图案化金属的图案化金属层的边缘上向上逐渐变细的氧化层。 然后，在从图案化的金属层掩蔽和蚀刻氧化物层之后，图案化的金属层和周围的氧化物层形成基本平坦的层，被图案化层的边缘处的小的剩余的氧化物突起中断。 这些小的剩余氧化物突起可能太小而不能显着地扰乱另外的氧化物或其它层的平坦度，或者可以通过施加另一HDP CVD氧化物膜进一步减轻它们。

    Bulk Acoustic Resonators with Multi-Layer Electrodes
    4.
    发明申请
    Bulk Acoustic Resonators with Multi-Layer Electrodes 有权
    具有多层电极的散音声谐振器

    公开(公告)号：US20090302973A1

    公开(公告)日：2009-12-10

    申请号：US12135431

    申请日：2008-06-09

    申请人： David Hart ,  Sudarsan Uppili ,  Guillaume Bouche

    发明人： David Hart ,  Sudarsan Uppili ,  Guillaume Bouche

    IPC分类号： H03H9/54

    CPC分类号： H03H9/171 ,  H03H9/02149 ,  H03H9/131 ,  H03H9/175 ,  H03H9/584 ,  H03H9/589

    摘要： Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W.

    摘要翻译： 具有用于体声波（BAW）谐振器装置的多层电极的体声共振器。 公开了各种电极组合。 本发明在使用Mo或双层Al和W的现有技术解决方案中，以keff2和电阻为基础提供了从1800MHz到4GHz的共振频率下的更好的折中。

    LDMOS with field plate connected to gate
    5.
    发明授权
    LDMOS with field plate connected to gate 有权
    LDMOS与场板连接到门

    公开(公告)号：US09450074B1

    公开(公告)日：2016-09-20

    申请号：US13194210

    申请日：2011-07-29

    申请人： Fanling Hsu Yang ,  Timothy K. McGuire ,  Sudarsan Uppili ,  Guillaume Bouche

    发明人： Fanling Hsu Yang ,  Timothy K. McGuire ,  Sudarsan Uppili ,  Guillaume Bouche

    IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66681 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

    摘要： Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

    摘要翻译： 描述了半导体器件，例如横向扩散的金属氧化物半导体（LDMOS）器件，其具有连接到器件的栅极的场板。 在一个或多个实施方案中，半导体器件包括具有第一导电类型的源极区和第一导电类型的漏极区的衬底。 栅极位于表面上并且在源极区域和漏极区域之间。 栅极被配置为接收电压，使得可以至少部分地在栅极下方形成导电区域，以允许多数载流子在源极区域和漏极区域之间行进。 该装置还包括至少部分地定位在栅极上并连接到栅极的场板。 场板被配置为当电压施加到栅极时，使在源极区域和漏极区域之间产生的电场成形。

    LDMOS with thick interlayer-dielectric layer
    6.
    发明授权
    LDMOS with thick interlayer-dielectric layer 有权
    LDMOS具有较厚的层间介电层

    公开(公告)号：US09171916B1

    公开(公告)日：2015-10-27

    申请号：US13272301

    申请日：2011-10-13

    申请人： David L. Snyder ,  Sudarsan Uppili ,  Guillaume Bouche

    发明人： David L. Snyder ,  Sudarsan Uppili ,  Guillaume Bouche

    IPC分类号： H01L29/40 ,  H01L21/8238

    CPC分类号： H01L29/402 ,  H01L21/82385 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

    摘要翻译： 描述了诸如LDMOS器件的半导体器件，其包括具有至少两个和一个（2.5）微米厚度的层间介电层（ILD）区域以增加最大击穿电压。 在一个或多个实施方案中，半导体器件包括具有靠近衬底表面形成的源区和漏区的衬底。 栅极位于表面上并且在源极区域和漏极区域之间。 在器件的表面和栅极上形成具有至少两个半（2.5）微米厚度的ILD区域。 该装置还包括一个或多个场板，其配置成当电压施加到栅极时，使在源极区域和漏极区域之间产生的电场成形。

    Integrated monolithic galvanic isolator
    7.
    发明授权
    Integrated monolithic galvanic isolator 有权
    集成单片电流隔离器

    公开(公告)号：US09209091B1

    公开(公告)日：2015-12-08

    申请号：US13198833

    申请日：2011-08-05

    申请人： David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

    发明人： David Harper ,  Sudarsan Uppili ,  Fanling Hsu Yang ,  David L. Snyder ,  Christopher S. Blair ,  Guillaume Bouche

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1211

    摘要： A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.

    摘要翻译： 描述了包括形成在绝缘体上半导体晶片上的第一电路和第二电路的半导体器件。 绝缘体上半导体晶片具有形成在绝缘材料的掩埋层上的半导体材料层，其形成在材料的支撑层上。 在半导体绝缘体晶片上形成宽的深沟槽，以将第一电路与第二电路电隔离。 第一电路和第二电路耦合在一起，用于在电隔离的电路之间交换能量。

    Piezoelectric deposition for BAW resonators
    8.
    发明申请
    Piezoelectric deposition for BAW resonators 审中-公开
    用于BAW谐振器的压电沉积

    公开(公告)号：US20090053401A1

    公开(公告)日：2009-02-26

    申请号：US11895454

    申请日：2007-08-24

    申请人： Sudarsan Uppili ,  Guillaume Bouche ,  Akhtar Mirfazli ,  Nicholas S. Argenti

    发明人： Sudarsan Uppili ,  Guillaume Bouche ,  Akhtar Mirfazli ,  Nicholas S. Argenti

    IPC分类号： B05D5/12

    CPC分类号： C23C14/0617 ,  H01L41/319 ,  H03H3/02 ,  H03H9/175 ,  H03H2003/025

    摘要： Piezoelectric deposition for BAW resonators wherein a thin amorphous layer of AlN over the bottom electrode before depositing a second layer of AlN over the amorphous layer of AlN, the depositing occurring at a temperature allowing the deposited AlN to self-organize into a desired columnar phase. The bottom electrode may have acoustic isolation thereunder, such as a Bragg mirror. Various details of the fabrication process are disclosed.

    摘要翻译： 用于BAW谐振器的压电沉积，其中在在AlN的非晶层上沉积第二AlN层之前，在底电极上方形成薄的非晶层AlN，沉积在允许沉积的AlN自组织成所需柱状相的温度下发生。 底部电极可以在其下方具有声学隔离，例如布拉格反射镜。 公开了制造工艺的各种细节。