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    Asymmetric junction field effect transistor
    4.
    发明授权
    Asymmetric junction field effect transistor 有权
    非对称结场效应晶体管

    公开(公告)号：US07943445B2

    公开(公告)日：2011-05-17

    申请号：US12388586

    申请日：2009-02-19

    申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    IPC分类号： H01L21/00 ,  H01L21/336

    CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

    摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

    摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

    Optimized device isolation
    5.
    发明授权
    Optimized device isolation 有权
    优化设备隔离

    公开(公告)号：US07868423B2

    公开(公告)日：2011-01-11

    申请号：US12269073

    申请日：2008-11-12

    申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    IPC分类号： H01L21/02

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

    DEEP TRENCH VARACTORS
    10.
    发明申请
    DEEP TRENCH VARACTORS 有权

    公开(公告)号：US20100155897A1

    公开(公告)日：2010-06-24

    申请号：US12342609

    申请日：2008-12-23

    申请人： David S. Collins ,  Robert M. Rassel ,  Eric Thompson

    发明人： David S. Collins ,  Robert M. Rassel ,  Eric Thompson

    IPC分类号： H01L29/93 ,  H01L21/20

    CPC分类号： H01L29/93 ,  H01L27/0805 ,  H01L27/0808 ,  H01L29/66181 ,  H01L29/945

    摘要： A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

    摘要翻译： 提供了与深沟槽电容器结构兼容的深沟槽变容二极管结构及其制造方法。 掩埋板层形成在第二深沟槽上，同时保护第一沟槽不形成任何掩埋的板层。 深沟槽的内部填充有导电材料以形成内部电极。 在第一深沟槽的外部和邻接部分形成至少一个掺杂阱，并构成至少一个外变容二极管电极。 多个掺杂阱可以并联连接以提供具有电容复杂电压依赖性的变容二极管。 掩埋板层和与其连接的另一个掺杂阱构成形成在第二深沟槽上的线性电容器的外部电极。