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    Physical address size selection and page size selection in an address translator
    1.
    发明授权
    Physical address size selection and page size selection in an address translator 失效
    地址翻译器中的物理地址大小选择和页面大小选择

    公开(公告)号：US5617554A

    公开(公告)日：1997-04-01

    申请号：US372805

    申请日：1994-12-23

    申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

    摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

    Physical address size selection and page size selection in an address translator
    2.
    发明授权
    Physical address size selection and page size selection in an address translator 失效
    地址翻译器中的物理地址大小选择和页面大小选择

    公开(公告)号：US5802605A

    公开(公告)日：1998-09-01

    申请号：US756184

    申请日：1996-11-25

    申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

    摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

    METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS
    4.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
    方法，装置和系统的交互式分析控制指令

    公开(公告)号：US20150032998A1

    公开(公告)日：2015-01-29

    申请号：US13997243

    申请日：2012-02-02

    申请人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

    发明人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

    摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

    摘要翻译： 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

    Apparatus and method for performing error correction in a multi-processor system
    6.
    发明授权
    Apparatus and method for performing error correction in a multi-processor system 失效
    用于在多处理器系统中执行纠错的装置和方法

    公开(公告)号：US5550988A

    公开(公告)日：1996-08-27

    申请号：US205604

    申请日：1994-03-01

    申请人： Nitin V. Sarangdhar ,  Konrad K. Lai

    发明人： Nitin V. Sarangdhar ,  Konrad K. Lai

    IPC分类号： G06F11/14 ,  G06F13/36

    CPC分类号： G06F13/36 ,  G06F11/1402

    摘要： In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.

    摘要翻译： 在具有第一处理器，第二处理器和将第一处理器耦合到第二处理器的总线的多处理器系统中，一种用于在保持锁原子性的同时校正与第一处理器相对应的错误信号的方法。 当检测到错误的事务时，第一处理器中止该事务并执行重试。 在重试时，仲裁过程在第一处理器和第二处理器之间进行仲裁以确定哪个处理器被授权访问总线。 如果在仲裁过程中检测到错误，则启动仲裁重新同步过程。 在仲裁重新同步过程中，总线请求被取消断言，然后重新仲裁。 在重新仲裁过程中，第一个处理器在另一个处理器之前发起其请求，以保持锁定原子性。

    Object lifetime control in an object-oriented memory protection mechanism
    7.
    发明授权
    Object lifetime control in an object-oriented memory protection mechanism 失效
    面向对象的存储器保护机制中的对象生命周期控制

    公开(公告)号：US5075848A

    公开(公告)日：1991-12-24

    申请号：US455585

    申请日：1989-12-22

    申请人： Konrad K. Lai ,  Frederick J. Pollack

    发明人： Konrad K. Lai ,  Frederick J. Pollack

    IPC分类号： G06F9/44 ,  G06F12/02 ,  G06F12/14

    CPC分类号： G06F9/4428 ,  G06F12/1475 ,  G06F12/023 ,  G06F2216/09

    摘要： An object-oriented computer architecture in which access descriptors include an object index for selecting an object in the address space, and a rights field specifying the permissible operations on a bi-paged object selected by the access descriptor. A local object lifetime bit is provided in the encoded fields portion of access descriptors, object descriptors, and page table entries to determine the lifetime of an object. The AD lifetime bit in the encoded fields of AD is compared in OTE Lifetime Check Logic with the destination object lifetime, the OTE local bit in the encoded fields of the OTE access descriptor. The OTE local bit in the encoded fields of the OTE is compared in PDTE Lifetime Check Logic with the destination object lifetime, the PDTE local bit in the encoded fields of the PDTE access descriptor. The PDTE local bit in the encoded fields of the PDTE is compared in PTE Lifetime Check Logic with the destination object lifetime, the PTE local bit in the encoded fields of the PTE access descriptor. If any of these checks fails, a protection lifetime fault is asserted.

    摘要翻译： 一种面向对象的计算机体系结构，其中访问描述符包括用于选择地址空间中的对象的对象索引，以及权限字段，其指定由访问描述符选择的双页对象的允许操作。 在访问描述符，对象描述符和页表项的编码字段部分中提供本地对象生存期，以确定对象的生命周期。 在OTE生命周期校验逻辑与目标对象寿命（OTE访问描述符的编码字段中的OTE本地位）比较AD的编码字段中的AD生存位。 OTE的编码字段中的OTE本地位在PDTE Lifetime Check Logic中与目标对象生命周期（PDTE访问描述符的编码字段中的PDTE本地位）进行比较。 PDTE的编码字段中的PDTE本地位在PTE终生校验逻辑中与目标对象生命周期（PTE访问描述符的编码字段中的PTE本地位）进行比较。 如果这些检查中有任何一个失败，则保护生命周期故障被断言。

    METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS
    10.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
    方法，装置和系统的交互式分析控制指令

    公开(公告)号：US20140379996A1

    公开(公告)日：2014-12-25

    申请号：US13997245

    申请日：2012-02-02

    申请人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

    发明人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

    IPC分类号： G06F9/52 ,  G06F12/08 ,  G06F9/46

    摘要： An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.

    摘要翻译： 这里描述了一种用于提供推测逃逸指令的装置和方法。 具体地，本文描述了显式的非事务性加载操作。 在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。 然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。 同样，也提供非事务存储。 这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。 并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。 换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。