公开(公告)号：US20130320286A1

公开(公告)日：2013-12-05

申请号：US13905822

申请日：2013-05-30

Applicant: Dong-soo LEE ,  Myoung-jae LEE ,  U-in CHUNG

Inventor： Dong-soo LEE ,  Myoung-jae LEE ,  U-in CHUNG

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer.

Abstract translation: 开关元件包括：第一电极; 第二电极; 以及在所述第一电极和所述第二电极之间的含硅的仲氮化物层。 开关装置包括：第一电极和第二电极之间的阈值开关材料层。 阈值开关材料层包括阳离子金属元素，硫属元素，硅元素和氮元素。 存储器件包括：彼此平行布置的多个第一布线; 多个第二布线，穿过第一配线，彼此平行布置; 以及形成在所述多个第一布线和所述多个第二布线的每个交叉点处的存储单元。 存储单元包括具有含硅的恰氮氮化物层，中间电极和存储层的层压体。

公开(公告)号：US20160172450A1

公开(公告)日：2016-06-16

申请号：US15050867

申请日：2016-02-23

Applicant: Dong-soo LEE ,  Myoung-jae LEE ,  Seong-ho CHO ,  Mohammad Rakib UDDIN ,  David SEO ,  Moon-seung YANG ,  Sang-moon LEE ,  Sung-hun LEE ,  Ji-hyun HUR ,  Eui-chul HWANG

Inventor： Dong-soo LEE ,  Myoung-jae LEE ,  Seong-ho CHO ,  Mohammad Rakib UDDIN ,  David SEO ,  Moon-seung YANG ,  Sang-moon LEE ,  Sung-hun LEE ,  Ji-hyun HUR ,  Eui-chul HWANG

IPC: H01L29/34 ,  H01L21/322

CPC classification number: H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

公开(公告)号：US20130051125A1

公开(公告)日：2013-02-28

申请号：US13590978

申请日：2012-08-21

Applicant: Man CHANG ,  Young-bae KIM ,  Chang-jung KIM ,  Myoung-jae LEE ,  Seong-jun PARK ,  Ji-hyun HUR ,  Dong-soo LEE ,  Chang-bum LEE ,  Seung-ryul LEE

Inventor： Man CHANG ,  Young-bae KIM ,  Chang-jung KIM ,  Myoung-jae LEE ,  Seong-jun PARK ,  Ji-hyun HUR ,  Dong-soo LEE ,  Chang-bum LEE ,  Seung-ryul LEE

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/00 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56

Abstract: According to an example embodiment, a method of operating a semiconductor device having a variable resistance device includes: applying a first voltage to the variable resistance device to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value; sensing a first current flowing through the variable resistance device to which the first voltage is applied; determining a second voltage used for changing the variable resistance device from the second resistance value to the first resistance value, based on a dispersion of the sensed first current; and applying the determined second voltage to the variable resistance device.

Abstract translation: 根据示例性实施例，一种操作具有可变电阻器件的半导体器件的方法包括：向可变电阻器件施加第一电压以将可变电阻器件的电阻值从第一电阻值改变为第二电阻值， 与第一电阻值不同; 感测流过施加有第一电压的可变电阻装置的第一电流; 基于感测到的第一电流的偏差，确定用于将可变电阻器件从第二电阻值改变为第一电阻值的第二电压; 以及将所确定的第二电压施加到所述可变电阻装置。

公开(公告)号：US20120161821A1

公开(公告)日：2012-06-28

申请号：US13313720

申请日：2011-12-07

Applicant: Man CHANG ,  Young-bae KIM ,  Chang-jung KIM ,  Myoung-jae LEE ,  Ji-hyun HUR ,  Dong-soo LEE ,  Chang-bum LEE ,  Seung-ryul LEE

Inventor： Man CHANG ,  Young-bae KIM ,  Chang-jung KIM ,  Myoung-jae LEE ,  Ji-hyun HUR ,  Dong-soo LEE ,  Chang-bum LEE ,  Seung-ryul LEE

IPC: H03B1/00 ,  H01C7/10

CPC classification number: G11C13/0069 ,  G11C11/5685 ,  G11C13/0064 ,  G11C2013/0073

Abstract: A method of operating a semiconductor device that includes a variable resistance device, the method including applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value; sensing first current flowing through the variable resistance device to which the first voltage is applied; determining whether the first current falls within a predetermined range of current; and if the first current does not fall within the first range of current, applying an additional first voltage that is equal to the first voltage to the variable resistance device.

Abstract translation: 一种操作包括可变电阻器件的半导体器件的方法，所述方法包括向可变电阻器件施加第一电压以便将可变电阻器件的电阻值从第一电阻值改变为第二电阻值，该第二电阻值是 不同于第一个电阻值; 感测流过施加有第一电压的可变电阻装置的第一电流; 确定第一电流是否落在预定的电流范围内; 并且如果所述第一电流不在所述第一电流范围内，则向所述可变电阻装置施加等于所述第一电压的附加第一电压。

公开(公告)号：US20070148451A1

公开(公告)日：2007-06-28

申请号：US11550121

申请日：2006-10-17

Applicant: Sung-ho PARK ,  Myoung-jae LEE ,  June-mo KOO ,  Bum-seok SEO

Inventor： Sung-ho PARK ,  Myoung-jae LEE ,  June-mo KOO ,  Bum-seok SEO

IPC: B32B9/00 ,  C23C16/00

CPC classification number: C23C16/26 ,  B82Y10/00 ,  B82Y30/00 ,  D01F9/127 ,  H01J9/025 ,  H01J2201/30469 ,  H01J2329/00 ,  Y10T428/2918

Abstract: A method of forming carbon fibers at a low temperature below 450° C. using an organic-metal evaporation method is provided. The method includes: heating a substrate and maintaining the substrate at a temperature of 200 to 450° C. after loading the substrate into a reaction chamber; preparing an organic-metal compound containing Ni; forming an organic-metal compound vapor by vaporizing the organic-metal compound; and forming carbon fibers on the substrate by facilitating a chemical reaction between the organic-metal compound vapor and a reaction gas containing ozone in the reaction chamber.

Abstract translation: 提供了使用有机金属蒸发法在低于450℃的低温下形成碳纤维的方法。 该方法包括：将基板加载到反应室中之后，加热基板并将基板保持在200至450℃的温度; 制备含有Ni的有机金属化合物; 通过蒸发有机金属化合物形成有机金属化合物蒸气; 以及通过促进有机金属化合物蒸气和在反应室中含有臭氧的反应气体之间的化学反应，在基板上形成碳纤维。

公开(公告)号：US20150069517A1

公开(公告)日：2015-03-12

申请号：US14259569

申请日：2014-04-23

Applicant: Moon-seung YANG ,  Mohammad Rakib UDDIN ,  Myoung-jae LEE ,  Sang-moon LEE ,  Sung-hun LEE ,  Seong-ho CHO

Inventor： Moon-seung YANG ,  Mohammad Rakib UDDIN ,  Myoung-jae LEE ,  Sang-moon LEE ,  Sung-hun LEE ,  Seong-ho CHO

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092

Abstract: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.

Abstract translation: 提供互补金属氧化物半导体（CMOS）器件及其制造方法。 在CMOS器件中，在硅衬底上设置缓冲层，并且在缓冲层上设置包括III-V族材料的第一层。 包含IV族材料的第二层设置在缓冲层或硅衬底上，同时与第一层间隔开。

公开(公告)号：US20150115321A1

公开(公告)日：2015-04-30

申请号：US14510354

申请日：2014-10-09

Applicant: Moon-seung YANG ,  Rakib Uddin MOHAMMAD ,  Myoung-jae LEE ,  Sang-moon LEE ,  Sung-hun LEE ,  Seong-ho CHO

Inventor： Moon-seung YANG ,  Rakib Uddin MOHAMMAD ,  Myoung-jae LEE ,  Sang-moon LEE ,  Sung-hun LEE ,  Seong-ho CHO

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L27/092

Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Abstract translation: 公开了一种衬底结构，包括衬底结构的互补金属氧化物半导体（CMOS）器件以及制造CMOS器件的方法，其中衬底结构包括：衬底，由材料形成的至少一个种子层 包括硼（B）和/或磷（P），以及种子层上的缓冲层。 该衬底结构使得可以减小缓冲层的厚度并且还改善由衬底结构形成的半导体器件的性能特性。

公开(公告)号：US20130252395A1

公开(公告)日：2013-09-26

申请号：US13892881

申请日：2013-05-13

Applicant: Sun-ae SEO ,  Young-soo PARK ,  Ran-Ju JUNG ,  Myoung-jae LEE ,  Dong-chul KIM ,  Seung-eon AHN

Inventor： Sun-ae SEO ,  Young-soo PARK ,  Ran-Ju JUNG ,  Myoung-jae LEE ,  Dong-chul KIM ,  Seung-eon AHN

IPC: H01L45/00

CPC classification number: H01L45/165 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM. A RRAM according to example embodiments may include a lower electrode, which may be formed on a lower structure (e.g., substrate). A resistive layer may be formed on the lower electrode, wherein the resistive layer may include a transition metal dopant. An upper electrode may be formed on the resistive layer. Accordingly, the transition metal dopant may form a filament in the resistive layer that operates as a current path.

Abstract translation: 示例实施例涉及电阻随机存取存储器（RRAM）和制造RRAM的方法。 根据示例性实施例的RRAM可以包括下电极，其可以形成在下结构（例如，衬底）上。 电阻层可以形成在下电极上，其中电阻层可以包括过渡金属掺杂剂。 上电极可以形成在电阻层上。 因此，过渡金属掺杂剂可以在作为电流路径工作的电阻层中形成丝。

公开(公告)号：US20090095985A1

公开(公告)日：2009-04-16

申请号：US12155511

申请日：2008-06-05

Applicant: Chang-bum LEE ,  Young-soo PARK ,  Myoung-jae LEE ,  Stefanovich GENRIKH ,  Ki-hwan KIM

Inventor： Chang-bum LEE ,  Young-soo PARK ,  Myoung-jae LEE ,  Stefanovich GENRIKH ,  Ki-hwan KIM

IPC: H01L27/10

CPC classification number: G11C13/0007 ,  G11C17/14 ,  G11C17/165 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided may be a multi-layer electrode, a cross point resistive memory array and method of manufacturing the same. The array may include a plurality of first electrode lines arranged parallel to each other; a plurality of second electrode lines crossing the first electrode lines and arranged parallel to each other; and a first memory resistor at intersections between the first electrode lines and the second electrode lines, wherein at least one of the first electrode lines and the second electrode lines have a multi-layer structure including a first conductive layer and a second conductive layer formed of a noble metal.

Abstract translation: 提供可以是多层电极，交叉点电阻存储器阵列及其制造方法。 阵列可以包括彼此平行布置的多个第一电极线; 与第一电极线交叉并且彼此平行布置的多个第二电极线; 以及第一电极线和第二电极线之间的交点处的第一存储电阻器，其中第一电极线和第二电极线中的至少一个具有包括第一导电层和第二导电层的第二导电层的多层结构， 贵金属。