公开(公告)号：US10811411B1

公开(公告)日：2020-10-20

申请号：US16459678

申请日：2019-07-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L33/00 ,  H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US20170033181A1

公开(公告)日：2017-02-02

申请号：US14810574

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Bharat V. Krishnan ,  Jody A. Fronheiser

IPC: H01L29/10 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/1054 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.

Abstract translation: 本文中公开的一种说明性方法包括在衬底翅片腔中单独形成不同半导体材料的交替层，以在凹陷衬底鳍上方形成多层鳍，其中形成不同半导体材料的各层 到最终厚度小于所形成的不同半导体材料的层的临界厚度，使绝缘材料层凹陷，以便将多层鳍片的至少一部分暴露在层的凹陷的上表面上方 绝缘材料并围绕暴露的多层鳍片的至少一部分形成栅极结构。

公开(公告)号：US10121706B2

公开(公告)日：2018-11-06

申请号：US15361809

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rinus T. P. Lee ,  Bharat V. Krishnan ,  Hui Zang ,  Matthew W. Stoker

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/32 ,  H01L27/092

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

公开(公告)号：US10062692B1

公开(公告)日：2018-08-28

申请号：US15443381

申请日：2017-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shishir K. Ray ,  Bharat V. Krishnan ,  Jinping Liu ,  Meera S. Mohan ,  Joseph K. Kassim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306 ,  H01L29/167 ,  H01L21/285 ,  H01L29/45

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

公开(公告)号：US20150214345A1

公开(公告)日：2015-07-30

申请号：US14164368

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jinping Liu ,  Churamani Gaire ,  Mariappan Hariharaputhiran ,  Andy Chih-Hung Wei ,  Bharat V. Krishnan ,  Cuiqin Xu ,  Michael Ganz

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/88 ,  H01L29/73 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66151 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7311 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/88

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract translation: 提供了用于在集成电路（IC）器件（例如，金属氧化物半导体场效应晶体管（MOSFET））中隔离源极和漏极区域的方法。 具体地，该器件包括形成在衬底上的栅极结构，与栅极结构相邻嵌入在衬底内的源极和漏极（S / D）以及S / D和衬底之间的衬里层（例如，硅 - 碳） 。 在一种方法中，衬垫层也形成在S / D的顶部。 因此，形成在接合部中的衬垫层防止掺杂剂从源极/漏极扩散。

公开(公告)号：US20150097197A1

公开(公告)日：2015-04-09

申请号：US14045983

申请日：2013-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Ganz ,  Johannes M. van Meer ,  Bharat V. Krishnan

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.

Abstract translation: 本发明的实施例提供了改进的finFET和制造方法。 Σ型空腔与n型finFET一起使用，以允许多个外延层邻近finFET栅极设置。 在一些实施例中，可以使用应力记忆技术在外延层中形成堆垛层错。

公开(公告)号：US10211045B1

公开(公告)日：2019-02-19

申请号：US15878502

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rishikesh Krishnan ,  Joseph K. Kassim ,  Bharat V. Krishnan ,  Joseph F. Shepard, Jr. ,  Rinus Tek Po Lee ,  Yiheng Xu

IPC: H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

公开(公告)号：US08912085B1

公开(公告)日：2014-12-16

申请号：US14017409

申请日：2013-09-04

Applicant: GlobalFoundries Inc.

Inventor： Bongki Lee ,  Bharat V. Krishnan ,  Jinping Liu

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/49 ,  H01L21/283 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513

Abstract: A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.

Abstract translation: 公开了一种能够提供附加阈值电压裕度而不牺牲门可靠性的门堆栈集成过程和所得到的器件的方法。 实施例包括在栅极沟槽中保形地形成边缘调整层，在边缘调整层上形成金属覆盖层，并在金属覆盖层上形成n型功函数（nWF）金属层。

公开(公告)号：US20210005601A1

公开(公告)日：2021-01-07

申请号：US16942816

申请日：2020-07-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US10134876B2

公开(公告)日：2018-11-20

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. Krishnan ,  Timothy J. McArdle ,  Rinus Tek Po Lee ,  Shishir K. Ray ,  Akshey Sehgal

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.