公开(公告)号：US10020202B2

公开(公告)日：2018-07-10

申请号：US15099641

申请日：2016-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Donghun Kang ,  Balaji Kannan ,  Jinping Liu

IPC: H01L21/308 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second region; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

公开(公告)号：US20170358581A1

公开(公告)日：2017-12-14

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US09960118B2

公开(公告)日：2018-05-01

申请号：US15001956

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Donghun Kang ,  Neal A. Makela ,  Christopher C. Parks

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/76846

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

公开(公告)号：US09754945B2

公开(公告)日：2017-09-05

申请号：US14452762

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/92

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US10483205B2

公开(公告)日：2019-11-19

申请号：US15901979

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Donghun Kang ,  Neal A. Makela ,  Christopher C. Parks

IPC: H01L21/768 ,  H01L23/532

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

公开(公告)号：US10083967B2

公开(公告)日：2018-09-25

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L21/764

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US09269607B2

公开(公告)日：2016-02-23

申请号：US14306598

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/308 ,  H01L21/321 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

Abstract translation: 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片前侧上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

公开(公告)号：US20180182711A1

公开(公告)日：2018-06-28

申请号：US15901979

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Donghun Kang ,  Neal A. Makela ,  Christopher C. Parks

IPC: H01L23/532 ,  H01L21/768

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

公开(公告)号：US20170207175A1

公开(公告)日：2017-07-20

申请号：US15001956

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Donghun Kang ,  Neal A. Makela ,  Christopher C. Parks

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/76846

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.