公开(公告)号：US09905673B2

公开(公告)日：2018-02-27

申请号：US15620082

申请日：2017-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin Peng ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US20150270142A1

公开(公告)日：2015-09-24

申请号：US14219039

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huang Liu ,  Wen-Pin Peng ,  Jean-Baptiste Laloe

IPC: H01L21/321 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/285 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L21/321 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

Abstract translation: 本发明的方面涉及用于形成诸如具有改善的性能的具有金属栅极的场效应晶体管（FET）的半导体器件的方法。 在半导体器件中的基板上形成金属栅极。 进一步处理可能导致形成金属栅极的金属中的不期望的氧化。 可以使用还原剂去除形成金属栅极的金属，留下基本上未被氧化的表面。

公开(公告)号：US20140131881A1

公开(公告)日：2014-05-15

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US09396995B1

公开(公告)日：2016-07-19

申请号：US14634080

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Garo Derderian ,  Wen-Pin Peng

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/263 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/49

CPC classification number: H01L21/7684 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/456

Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.

Abstract translation: 提供了一种在MOL中形成金属化接触的方法。 实施例包括通过ILD形成TT到S / D区域; 在TT的侧表面上形成SiOC，SiCN或SiON层; 以0°角执行GCIB垂直蚀刻; 通过角度PAI将Si注入TT; 通过Ar溅射和远程等离子体辅助干蚀刻工艺去除TT的一部分; 在TT底部的S / D区域形成NiSi; 并用NiSi上的接触金属填充TT。

公开(公告)号：US20150318204A1

公开(公告)日：2015-11-05

申请号：US14265536

申请日：2014-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yong M. Lee ,  Yue Hu ,  Wen-Pin Peng

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L21/76831 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.

Abstract translation: 本发明的方面涉及防止半导体器件中的接触侵蚀的方法。 接触沟槽的第一部分可以被蚀刻到半导体器件的源极 - 漏极区域的中途。 电介质衬垫可以沉积在该沟槽中。 可以在衬里的沟槽上执行第二蚀刻，以在接近沟槽沟道的其余部分到源极 - 漏极区域蚀刻接触沟槽沟道。 这在第二次蚀刻之后留下留在沟槽中的介质衬垫的一部分（例如，覆盖沟槽的垂直壁）。

公开(公告)号：US09711619B1

公开(公告)日：2017-07-18

申请号：US15000111

申请日：2016-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin Peng ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US09385030B2

公开(公告)日：2016-07-05

申请号：US14265536

申请日：2014-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yong M. Lee ,  Yue Hu ,  Wen-Pin Peng

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L21/76831 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.

Abstract translation: 本发明的方面涉及防止半导体器件中的接触侵蚀的方法。 接触沟槽的第一部分可以被蚀刻到半导体器件的源极 - 漏极区域的中途。 电介质衬垫可以沉积在该沟槽中。 可以在衬里的沟槽上执行第二蚀刻，以在接近沟槽沟道的其余部分到源极 - 漏极区域蚀刻接触沟槽沟道。 这在第二次蚀刻之后留下留在沟槽中的介电衬垫的一部分（例如，覆盖沟槽的垂直壁）。

公开(公告)号：US09123783B2

公开(公告)日：2015-09-01

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US10854472B2

公开(公告)日：2020-12-01

申请号：US14219039

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huang Liu ,  Wen-Pin Peng ,  Jean-Baptiste Laloe

IPC: H01L21/312 ,  H01L21/321 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768

Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

公开(公告)号：US09607989B2

公开(公告)日：2017-03-28

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Yue Hu ,  Xin Wang ,  Yong Meng Lee ,  Wen-Pin Peng ,  Lun Zhao ,  Wei-Hua Tong

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.