公开(公告)号：US09466604B2

公开(公告)日：2016-10-11

申请号：US14540724

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Myungjun Lee ,  Ryan Ryoung-Han Kim ,  Jongwook Kye

IPC: H01L29/66 ,  H01L21/82 ,  H01L27/11 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract translation: 公开了用于利用附加金属层的金属段作为通孔的着陆焊盘以及IC器件中的触点之间的局部互连以及所产生的器件的方法。 实施例包括在集成电路器件中形成连接到衬底上的晶体管的源极/漏极和栅极触点，每个触点具有带有第一区域的上表面; 在触头的上表面处的平面中形成金属段，每个金属段与一个或多个触点接触并具有大于第一区的第二区; 以及在一个或多个金属段和第一金属层的一个或多个第一段之间形成一个或多个通孔。

公开(公告)号：US20200176587A1

公开(公告)日：2020-06-04

申请号：US16777243

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Hui Zang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.

公开(公告)号：US10236215B1

公开(公告)日：2019-03-19

申请号：US15791711

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

公开(公告)号：US09627389B1

公开(公告)日：2017-04-18

申请号：US15003304

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Lei Yuan ,  Srinivasa Banna

IPC: H01L21/311 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Methods to utilize efficient processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing mandrels separated from each other across two adjacent bit-cells on an upper surface of a dielectric layer on an upper surface of a silicon (Si) layer; forming first spacers on opposite sides of each mandrel; forming second spacers on exposed sides of the first spacers; removing the mandrels; removing exposed sections of the dielectric layer; removing the first and second spacers; forming fin-spacers on opposite sides of remaining sections of the dielectric layer; removing the remaining sections of the dielectric layer; removing exposed sections of the Si layer; and removing the fin-spacers to reveal Si fins.

公开(公告)号：US09105510B2

公开(公告)日：2015-08-11

申请号：US14461745

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

IPC: H01L21/8234 ,  H01L27/11 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract translation: 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 去除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US08962483B2

公开(公告)日：2015-02-24

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/3065 ,  H01L21/308 ,  G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US09711511B1

公开(公告)日：2017-07-18

申请号：US15193867

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim ,  Motoi Ichihashi ,  Youngtag Woo ,  Deepak Nayak

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/7827

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

公开(公告)号：US09472464B1

公开(公告)日：2016-10-18

申请号：US15060691

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Lei Yuan ,  Youngtag Woo ,  Yan Wang ,  Jongwook Kye

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract translation: 公开了在翅片生成中形成和使用合并间隔物的方法以及所得装置。 实施例包括提供在Si层上相邻的单元彼此分开的第一和第二心轴; 在第一和第二心轴的相对侧分别形成第一和第二虚拟间隔物和第三和第四虚拟间隔物; 通过块掩模去除第一和第四虚拟间隔物和第二和第三虚拟间隔物的一部分; 在心轴的每个暴露侧上并在第二和第三虚拟间隔件之间形成第一间隔件，形成合并间隔件; 去除心轴; 去除合并间隔物的一部分; 在第一间隔件和合并间隔件的所有暴露侧上形成第二间隔件; 去除合并间隔物和第一间隔物; 通过所述第二间隔物去除所述Si层的暴露部分; 并且移除第二间隔件以露出Si散热片。

公开(公告)号：US09406616B2

公开(公告)日：2016-08-02

申请号：US14561359

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Ryan Ryoung-han Kim

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L23/535 ,  H01L27/11 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract translation: 公开了一种形成具有均匀的规则形状的栅极触点的半导体器件的方法以及所得到的器件。 实施例包括在基板上形成彼此相邻的第一和第二栅电极; 在所述第一和第二栅电极之间的所述衬底上形成至少一个沟槽硅化物（TS）; 在第一栅电极上形成栅极接触，栅接触具有规则形状; 在所述第一和第二栅电极之间的沟槽硅化物上形成源极/漏极接触，其中所述源极/漏极接触部的上部与所述栅极接触件的上部重叠。

公开(公告)号：US09324722B1

公开(公告)日：2016-04-26

申请号：US14797757

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Lei Yuan ,  Jongwook Kye

IPC: H01L21/4763 ,  H01L27/11 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.

Abstract translation: 公开了一种利用切割掩模结合块掩模在IC器件中形成金属布线的方法。 实施例包括在氧化硅层的上表面上形成硬掩模层; 在所述硬掩模的上表面上形成间隔开的平行心轴; 在每个心轴的相对侧上形成间隔物，去除心轴，形成交替的心轴和非心轴空间; 在心轴和非心轴空间上形成阻挡掩模部分; 去除所述氧化硅的所述硬掩模暴露部分的暴露部分，去除所述阻挡掩模部分; 在所述硬掩模的上表面上形成具有比所述阻挡掩模部分更短的开口的切割掩模; 通过切割掩模开口去除硬掩模，去除切割掩模; 在氧化硅的暴露区域中形成空腔; 去除间隔物和任何剩余的硬掩模; 并在空腔中形成金属线。