公开(公告)号：US10691862B2

公开(公告)日：2020-06-23

申请号：US15644288

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Neha Nayyar ,  Daniel J. Dechene ,  David C. Pritchard ,  George J. Kluth

IPC: G06F30/394 ,  H01L23/522 ,  H01L21/8234

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

公开(公告)号：US09780002B1

公开(公告)日：2017-10-03

申请号：US15173766

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Brian Greene ,  Mahender Kumar ,  Daniel J. Dechene ,  Daniel Jaeger

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/26506 ,  H01L21/02118 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.

公开(公告)号：US10170309B2

公开(公告)日：2019-01-01

申请号：US15422689

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel J. Dechene ,  Geng Han

IPC: H01L21/00 ,  H01L27/11 ,  H01L21/033 ,  H01L27/02 ,  H01L27/118

Abstract: A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (CDU) of main critical (non-dummy) features at the same masking level.

公开(公告)号：US10833160B1

公开(公告)日：2020-11-10

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/82 ,  H01L21/033 ,  H01L21/027 ,  H01L21/306 ,  H01L29/417 ,  H01L27/088 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US20180337045A1

公开(公告)日：2018-11-22

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/0276 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76879

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US20200227350A1

公开(公告)日：2020-07-16

申请号：US16248317

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaladhi Mehta ,  Brian Greene ,  Daniel J. Dechene ,  Ahmed Hassan

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/76

Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.

公开(公告)号：US10332745B2

公开(公告)日：2019-06-25

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3065

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.