SILICON CONTROLLED RECTIFIERS
    3.
    发明公开

    公开(公告)号:US20240347528A1

    公开(公告)日:2024-10-17

    申请号:US18300161

    申请日:2023-04-13

    CPC classification number: H01L27/0262

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.

    PHOTODETECTORS ON FIN STRUCTURE
    4.
    发明公开

    公开(公告)号:US20240072184A1

    公开(公告)日:2024-02-29

    申请号:US17895599

    申请日:2022-08-25

    CPC classification number: H01L31/035281 H01L31/18 H01L31/028

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors and methods of manufacture. The structure includes: a trench structure in a semiconductor substrate; at least one fin structure comprising semiconductor material which extends from a bottom of the trench structure; a photodetector material within the trench structure and extends from the at least one fin structure; a first contact connected to and on a first side of the photodetector material; and a second contact connected to the semiconductor substrate on a second side of the photodetector material.

    HIGH VOLTAGE MOSFET DEVICE WITH IMPROVED BREAKDOWN VOLTAGE

    公开(公告)号:US20230290880A1

    公开(公告)日:2023-09-14

    申请号:US17692218

    申请日:2022-03-11

    CPC classification number: H01L29/7816 H01L29/0611

    Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

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