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    Method and system for accessing a nonvolatile memory via SPI ports
    3.
    发明授权
    Method and system for accessing a nonvolatile memory via SPI ports 有权

    公开(公告)号：US11755505B2

    公开(公告)日：2023-09-12

    申请号：US17674630

    申请日：2022-02-17

    申请人： GOWIN Semiconductor Corporation

    发明人： Jinghui Zhu

    IPC分类号： G06F13/16 ,  G06F13/42

    CPC分类号： G06F13/1668 ,  G06F13/4282

    摘要： A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

    Method and system for providing a sleep mode to a configurable logic block using an intermittent power saving logic
    6.
    发明授权
    Method and system for providing a sleep mode to a configurable logic block using an intermittent power saving logic 有权

    公开(公告)号：US11385709B2

    公开(公告)日：2022-07-12

    申请号：US17233344

    申请日：2021-04-16

    申请人： GOWIN Semiconductor Corporation, Ltd.

    发明人： Jinghui Zhu

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

    摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

    METHOD AND SYSTEM FOR ENHANCING PROGRAMMABILITY OF A FIELD-PROGRAMMABLE GATE ARRAY
    7.
    发明申请
    METHOD AND SYSTEM FOR ENHANCING PROGRAMMABILITY OF A FIELD-PROGRAMMABLE GATE ARRAY 有权

    公开(公告)号：US20220027071A1

    公开(公告)日：2022-01-27

    申请号：US16938771

    申请日：2020-07-24

    申请人： GOWIN Semiconductor Corporation

    发明人： Jinghui Zhu ,  Diwakar Chopperla

    IPC分类号： G06F3/06 ,  G06F9/4401

    摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

    METHOD AND SYSTEM FOR PROVIDING WORD ADDRESSABLE NONVOLATILE MEMORY IN A PROGRAMMABLE LOGIC DEVICE
    8.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING WORD ADDRESSABLE NONVOLATILE MEMORY IN A PROGRAMMABLE LOGIC DEVICE 有权

    公开(公告)号：US20210281264A1

    公开(公告)日：2021-09-09

    申请号：US17225022

    申请日：2021-04-07

    申请人： GOWIN Semiconductor Corporation

    发明人： Jinghui Zhu

    IPC分类号： H03K19/1776 ,  G11C13/00 ,  H03K19/17736 ,  G11C16/10 ,  G11C11/22 ,  G11C11/16 ,  H03K19/17724

    摘要： A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

    Programmable logic device with on-chip user non-volatile memory
    9.
    发明授权
    Programmable logic device with on-chip user non-volatile memory 有权

    公开(公告)号：US10990556B2

    公开(公告)日：2021-04-27

    申请号：US14831204

    申请日：2015-08-20

    申请人： Gowin Semiconductor Corporation, Ltd.

    发明人： Jinghui Zhu ,  San-Ta Kow

    IPC分类号： G06F13/40 ,  G06F13/10 ,  G06F13/16 ,  G06F9/445 ,  G06F15/78 ,  G06F9/4401

    摘要： The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

    Method and apparatus for providing field-programmable gate array (FPGA) integrated circuit (IC) package
    10.
    发明授权
    Method and apparatus for providing field-programmable gate array (FPGA) integrated circuit (IC) package 有权

    公开(公告)号：US11901895B2

    公开(公告)日：2024-02-13

    申请号：US17828037

    申请日：2022-05-31

    申请人： GOWIN Semiconductor Corporation, Ltd.

    发明人： Grant Thomas Jennings ,  Jinghui Zhu

    IPC分类号： H03K19/17736 ,  H03K19/17728

    CPC分类号： H03K19/1774 ,  H03K19/17728

    摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.