公开(公告)号：US10545821B2

公开(公告)日：2020-01-28

申请号：US15664874

申请日：2017-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ron M. Roth ,  Richard H. Henze

IPC: G06F11/00 ,  G06F11/10 ,  G11C13/00 ,  G11C29/52

Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m

公开(公告)号：US20190272886A1

公开(公告)日：2019-09-05

申请号：US15909337

申请日：2018-03-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Jeffrey Alan Lucas ,  Tommy Miles ,  James Ignowski ,  William L. Wilson ,  Richard H. Henze

IPC: G11C29/16 ,  G11C29/26 ,  G11C29/34 ,  G11C29/56 ,  G01R31/317

Abstract: In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.

公开(公告)号：US20170271408A1

公开(公告)日：2017-09-21

申请号：US15329896

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  Zhiyong Li ,  Richard H. Henze

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2418 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A method of forming a multi-layered selector of a memory cell is described. In the method, a memory element of the memory cell is formed. The memory element stores information. A multi-layered selector of the memory cell is formed by alternating deposition of at least a dielectric layer and a first diffusion layer. The first diffusion layer includes fast diffusive ions. The multi-layered selector is coupled to the memory element in a memory cell.

公开(公告)号：US20190034268A1

公开(公告)日：2019-01-31

申请号：US15664874

申请日：2017-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ron M. Roth ,  Richard H. Henze

IPC: G06F11/10 ,  G11C29/52 ,  G11C13/00

CPC classification number: G06F11/1068 ,  G11C7/1006 ,  G11C7/16 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/52 ,  G11C2213/77 ,  H03M13/05

Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a. crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m

公开(公告)号：US09847378B2

公开(公告)日：2017-12-19

申请号：US15306125

申请日：2014-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Xia Sheng ,  Yoocharn Jeon ,  Jianhua Yang ,  Hans S. Cho ,  Richard H. Henze

IPC: H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/73 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

公开(公告)号：US20170053968A1

公开(公告)日：2017-02-23

申请号：US15306125

申请日：2014-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Xia Sheng ,  Yoocharn Jeon ,  Jianhua Yang ,  Hans S. Cho ,  Richard H. Henze

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/73 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Abstract translation: 电阻式存储器件包括与导体接触的导体和电阻式存储器堆叠。 电阻式存储器堆叠包括多组分电极和开关区域。 多组分电极包括具有表面的基极电极和基极电极表面上的惰性材料电极，其形式为i）薄层，或ii）不连续的纳米岛。 当惰性材料电极为薄层形式时，开关区域与导体和惰性材料电极接触; 或者当惰性材料电极为不连续的纳米岛的形式时，开关区域与惰性材料电极接触导体，并与基极的氧化部分接触。

公开(公告)号：US20160343432A1

公开(公告)日：2016-11-24

申请号：US15113914

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Richard H. Henze ,  Naveen Muralimanohar ,  Yoocharn Jeon ,  Martin Foltin ,  Erik Ordentlich ,  Gregg B. Lesartre ,  R. Stanley Williams

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: G11C13/004 ,  G11C5/025 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

Abstract translation: 具有多个延迟层的非易失性存储器件包括至少两个交叉存储器阵列，每个横向存储器阵列包括多个存储器单元，每个存储器单元连接到字线和位于交叉点的位线。 交叉开关存储器阵列每个具有不同的延迟。 交叉开关存储器阵列形成在单个管芯上。

公开(公告)号：US11061766B2

公开(公告)日：2021-07-13

申请号：US16712358

申请日：2019-12-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ron M. Roth ,  Richard H. Henze

IPC: G06F11/00 ,  G06F11/10 ,  G11C13/00 ,  G11C7/10 ,  G11C7/16 ,  H03M13/05 ,  G06F17/16 ,  G11C29/52

Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m

公开(公告)号：US09773547B2

公开(公告)日：2017-09-26

申请号：US15113914

申请日：2014-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Richard H. Henze ,  Naveen Muralimanohar ,  Yoocharn Jeon ,  Martin Foltin ,  Erik Ordentlich ,  Gregg B. Lesartre ,  R. Stanley Williams

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C5/02 ,  H01L23/528

CPC classification number: G11C13/004 ,  G11C5/025 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.