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公开(公告)号：US20100109756A1
公开(公告)日：2010-05-06
申请号：US12686430
申请日：2010-01-13
IPC分类号： G05F1/10
CPC分类号： G11C5/146 , G11C11/401 , G11C11/4074 , G11C29/02 , G11C29/026 , G11C29/028 , H01L2924/0002 , H01L2924/00
摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.
摘要翻译： 一种防止工作速度降低的基板电压控制技术，并且相对于低电压使用而抑制由于阈值电压较低导致的漏电流。 由于通过多个复制MOS晶体管检测阈值电压的中心值，并且控制衬底电压以控制阈值电压的中心值，从而可以满足操作速度的下限和上限 整个芯片的漏电流。 另一方面，在芯片工作期间动态地控制衬底电压，从而可以在芯片工作时降低阈值电压的中心值以提高速度，并且增加阈值电压的中心值 芯片运行后降低整个芯片的漏电流。
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公开(公告)号：US20090066390A1
公开(公告)日：2009-03-12
申请号：US12205668
申请日：2008-09-05
申请人： Akira IDE , Yasuhiro TAKAI , Tomonori SEKIGUCHI , Riichiro TAKEMURA , Satoru AKIYAMA , Hiroaki NAKAYA
发明人： Akira IDE , Yasuhiro TAKAI , Tomonori SEKIGUCHI , Riichiro TAKEMURA , Satoru AKIYAMA , Hiroaki NAKAYA
IPC分类号： H03H11/26
CPC分类号： H03K5/15033
摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.
摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m.T1 + n。（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m.T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n的精细定时信号（T2 / L）。 m和n的值可以由寄存器设置。
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公开(公告)号：US20080239865A1
公开(公告)日：2008-10-02
申请号：US12028788
申请日：2008-02-09
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。
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公开(公告)号：US20080055958A1
公开(公告)日：2008-03-06
申请号：US11976531
申请日：2007-10-25
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。
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公开(公告)号：US20090180343A1
公开(公告)日：2009-07-16
申请号：US12352347
申请日：2009-01-12
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
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公开(公告)号：US20090129136A1
公开(公告)日：2009-05-21
申请号：US12354549
申请日：2009-01-15
CPC分类号： G11C8/12 , G11C5/025 , G11C5/04 , G11C7/18 , G11C11/4097 , H01L25/0657 , H01L27/0207 , H01L27/10814 , H01L2224/4826 , H01L2924/13091 , H01L2924/00
摘要： If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package.In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.
摘要翻译： 如果通过使用纵横比为1:2的存储单元，以常规方式布置存储单元块以创建具有2的奇数功率的容量的存储芯片，则芯片将采取1：1的形状并变得难以 以1：2的形状包装。 此外，存储单元块的这种传统布局形成1：2形状会导致外围电路区域的区域受到存储块的限制，焊盘将被集中布置在芯片的中心部分中，并且布线成为 密封在芯片封装中的封装。 因此，在本发明中，将四个存储器块BANK0，BANK1，BANK2，BANK3，BANK3构造成L形，然后这些存储块被适当地组合并布置成构成近似1：2形状的芯片 长宽比。
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公开(公告)号：US20100277996A1
公开(公告)日：2010-11-04
申请号：US12028538
申请日：2008-02-08
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。
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公开(公告)号：US20120256157A1
公开(公告)日：2012-10-11
申请号：US13528132
申请日：2012-06-20
IPC分类号： H01L47/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
摘要翻译： 例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。
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公开(公告)号：US20070285975A1
公开(公告)日：2007-12-13
申请号：US11736252
申请日：2007-04-17
IPC分类号： G11C11/02
CPC分类号： H01L27/228 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb. Further, fluctuation of respective memory cells is suppressed by a driving method setting the amount of spin constant by bit line charge to suppress read disturb.
摘要翻译： 在使用自旋传递转矩的存储器中，通过在重写之前施加弱脉冲来减小重写电流使自旋状态变得不稳定。 利用电流在电流变得非线性地增加而与脉冲宽度对应的状态下进行高速运行的读取，以抑制干扰。 此外，通过利用位线电荷设定自旋常数的驱动方法来抑制各个存储单元的波动，以抑制读取干扰。
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公开(公告)号：US20120097912A1
公开(公告)日：2012-04-26
申请号：US13345231
申请日：2012-01-06
IPC分类号： H01L45/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
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