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1.发明授权Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device 有权半导体集成电路器件及半导体集成电路器件的制造方法公开(公告)号：US09287259B2
公开(公告)日：2016-03-15
申请号：US14111549
申请日：2012-04-09
IPC分类号： H01L27/088 , H01L29/66 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调节金属膜并将膜分量从它们引入高k栅极绝缘膜来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。
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2.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权半导体集成电路装置及制造半导体集成电路装置的方法公开(公告)号：US20140035055A1
公开(公告)日：2014-02-06
申请号：US14111549
申请日：2012-04-09
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。 这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。 因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。 然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。 根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。
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公开(公告)号：US20080113480A1
公开(公告)日：2008-05-15
申请号：US11939941
申请日：2007-11-14
IPC分类号： H01L21/8236
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/32155 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/823857
摘要： A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set so that the implanted ions may not break through the polysilicon gate.
摘要翻译： 用抗蚀剂掩模覆盖半导体衬底，然后通过光刻和干蚀刻形成用于暴露多晶硅栅极的整个上表面的开口。 此后，通过开口将氮离子注入到多晶硅栅极中。 此时的植入能量被设定为使得注入的离子不会穿过多晶硅栅极。
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公开(公告)号：US06777758B2
公开(公告)日：2004-08-17
申请号：US09754325
申请日：2001-01-05
IPC分类号： H01L2976
CPC分类号： H01L21/28512 , H01L21/76895 , H01L21/823493
摘要： P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.
摘要翻译： 具有不同杂质分布的P阱（11,12）相邻地形成在半导体衬底（50）的表面（50S）中。 在P阱（11,12）的表面（50S）中形成具有比P阱（11,12）低的电阻率的P型层（20），使得P阱（11,12）电 通过P型层（20）彼此连接。 接触件（31,32）分别填充形成在与P型层（20）接触的层间隔离膜（70）中的接触孔（70H1,70H2）。 触头（31,32）连接到导线（40）上。 电线（70）连接到规定电位，由此通过触点（31,32）和P型层（20）将P阱（11,12）固定到规定的电位。 因此，可以稳定地固定阱的电位，并且可以减少用于固定上述电位的元件的布局面积。
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公开(公告)号：US20100044802A1
公开(公告)日：2010-02-25
申请号：US12495070
申请日：2009-06-30
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7846
摘要： Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要翻译： 提供一种半导体器件，其可以形成具有接近设计尺寸的尺寸的元件区域，抑制类似于栅极引起的漏极泄漏的现象，并且进一步抑制通过导电的氧化对元件区域施加的压缩应力 电影; 以及半导体装置的制造方法。 沟槽在半导体基板的主表面上制成。 通过氧化每个沟槽的壁表面，在壁表面上形成第一氧化膜。 嵌入的导电膜被形成为嵌入到沟槽中。 嵌入的导电膜在含有活性氧化物质的气氛中被氧化，从而形成第二氧化膜。 通过CVD或涂布法在第二氧化物膜上形成第三氧化物膜。
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公开(公告)号：US20070138574A1
公开(公告)日：2007-06-21
申请号：US11563500
申请日：2006-11-27
IPC分类号： H01L29/76
CPC分类号： H01L21/823443 , H01L21/28114 , H01L21/823456 , H01L21/823468 , H01L21/823835 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.
摘要翻译： 具有不同栅极长度的多晶硅栅电极的顶端形成为等于高于侧壁的顶端的高度。 形成金属膜以覆盖多晶硅栅电极，然后通过热处理进行硅化。 由于多晶硅栅电极的顶端形成为低于侧壁的顶端，因此即使在精细栅极长度的情况下，硅侧反应也不会加速，并且以一维方式进行。 结果，即使使用具有不同栅极长度的多晶硅栅极，也可以稳定地形成具有均匀金属组成比的全硅化物栅电极。
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7.发明授权Semiconductor device with element isolation using impurity-doped insulator and oxynitride film 失效使用杂质掺杂绝缘体和氧氮化物膜的元件隔离的半导体器件公开(公告)号：US06744113B2
公开(公告)日：2004-06-01
申请号：US10377829
申请日：2003-03-04
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/823481
摘要： In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
摘要翻译： 在沟槽（2）中，氧氮化物膜（31ON1）和氧化硅膜（3101）位于掺杂氧化硅膜（31D）和衬底（1）之间，氧化硅膜（310）位于更靠近 到沟槽（2）的入口比掺杂的氧化硅膜（31D）。 氧氮化物膜（31ON1）通过利用氧化硅膜（3101）的氮化工艺形成。 沟槽（2）的入口附近被氧化硅膜（3101,3102）和氮氧化物膜（31ON1）所占据。
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公开(公告)号：US08592284B2
公开(公告)日：2013-11-26
申请号：US12495070
申请日：2009-06-30
IPC分类号： H01L21/76
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7846
摘要： Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.
摘要翻译： 提供一种半导体器件，其可以形成具有接近设计尺寸的尺寸的元件区域，抑制类似于栅极引起的漏极泄漏的现象，并且进一步抑制通过导电的氧化对元件区域施加的压缩应力 电影; 以及半导体装置的制造方法。 沟槽在半导体基板的主表面上制成。 通过氧化每个沟槽的壁表面，在壁表面上形成第一氧化膜。 嵌入的导电膜被形成为嵌入到沟槽中。 嵌入的导电膜在含有活性氧化物质的气氛中被氧化，从而形成第二氧化物膜。 通过CVD或涂布法在第二氧化物膜上形成第三氧化物膜。
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9.发明授权Semiconductor device with trench isolation having a diffusion preventing film and manufacturing method thereof 有权具有沟槽隔离的半导体器件具有防扩散膜及其制造方法公开(公告)号：US08587085B2
公开(公告)日：2013-11-19
申请号：US13286699
申请日：2011-11-01
申请人： Katsuyuki Horita
发明人： Katsuyuki Horita
CPC分类号： H01L21/76229 , H01L29/6659 , H01L29/7833
摘要： There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0≦x
摘要翻译： 提供了一种能够在由沟槽型元件隔离部分包围的有源区域中形成的场效应晶体管中提供期望的操作特性的技术。 元件隔离部分包括沟槽型元件隔离膜，各自包括硅膜或氧化硅膜的扩散防止膜，并且在沟槽型元件隔离膜的顶表面上形成厚度为10至20nm的氧化硅 形成在扩散防止膜的上表面上的厚度为0.5〜2nm的膜。 防扩散膜的组成为SiOx（0 @ x <2）。 沟槽型元件隔离膜和氧化硅膜的组成均为SiO 2。
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公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译： 为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一 层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。
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