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    Signal transmission system having a timing adjustment circuit
    4.
    发明授权
    Signal transmission system having a timing adjustment circuit 有权
    信号传输系统具有定时调整电路

    公开(公告)号：US06484268B2

    公开(公告)日：2002-11-19

    申请号：US09794084

    申请日：2001-02-28

    申请人： Hirotaka Tamura ,  Hisakatsu Araki ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Araki ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F104

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    Phase interpolator for a timing signal generating circuit
    8.
    发明授权
    Phase interpolator for a timing signal generating circuit 有权
    用于定时信号发生电路的相位内插器

    公开(公告)号：US08065553B2

    公开(公告)日：2011-11-22

    申请号：US12358861

    申请日：2009-01-23

    申请人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F1/24 ,  H03J7/04

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    Timing signal generating circuit with a master circuit and slave circuits
    9.
    发明授权
    Timing signal generating circuit with a master circuit and slave circuits 有权
    具有主电路和从电路的定时信号发生电路

    公开(公告)号：US07496781B2

    公开(公告)日：2009-02-24

    申请号：US10278800

    申请日：2002-10-24

    申请人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    发明人： Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Junji Ogawa

    IPC分类号： G06F1/04 ,  G05F1/12 ,  H03L7/06

    CPC分类号： H04L7/0337 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  H03K2005/00052 ,  H04L7/0025

    摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

    摘要翻译： 半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。 定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号 的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。 以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

    HYBRID CIRCUIT USING RESISTOR
    10.
    发明申请
    HYBRID CIRCUIT USING RESISTOR 审中-公开
    使用电阻的混合电路

    公开(公告)号：US20080187056A1

    公开(公告)日：2008-08-07

    申请号：US12048946

    申请日：2008-03-14

    申请人： Kohtaroh GOTOH ,  Hirotaka Tamura

    发明人： Kohtaroh GOTOH ,  Hirotaka Tamura

    IPC分类号： H04B3/00 ,  H04L23/00

    CPC分类号： H04L5/1423 ,  H04B3/03 ,  H04L25/0292

    摘要： A hybrid circuit includes a resistor inserted serially between a transmission line and an output driver for transmitting a signal; and a reception signal extraction unit for extracting only a reception signal from a signal existing in a transmission path by using a signal obtained from both ends of the resistor. The reception signal extraction unit can be constituted by, for example, two transconductance amplifiers for converting the input voltage into a current and a load resistor in which flows the current of a result of adding the output currents of the two amplifiers.

    摘要翻译： 混合电路包括串行地插入在传输线和用于发送信号的输出驱动器之间的电阻器; 以及接收信号提取单元，用于通过使用从电阻器的两端获得的信号从仅存在于传输路径中的信号中提取接收信号。 接收信号提取单元可以由例如用于将输入电压转换成电流的两个跨导放大器和加上两个放大器的输出电流的结果的电流的负载电阻构成。