公开(公告)号：US11556043B2

公开(公告)日：2023-01-17

申请号：US17348049

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Younghyun Kim ,  Didit Yudistira ,  Bernardette Kunert ,  Joris Van Campenhout ,  Maria Ioanna Pantouvaki

IPC: G02F1/225 ,  G02F1/21 ,  H01L29/66 ,  H01L29/94

Abstract: A monolithic integrated electro-optical phase modulator, a Mach-Zehnder modulator including one or more of the phase modulators, and method for fabricating the phase modulator by III-V-on-silicon semiconductor processing are provided. The phase modulator includes a silicon-based n-type substrate base layer, and a III-V n-type ridge waveguide for propagating light, wherein the ridge waveguide protrudes from and extends along the n-type substrate base layer. Further, the phase modulator includes one or more insulating layers provided on the ridge waveguide, wherein the one or more insulating layers have together a thickness of 1-100 nm, and a silicon-based p-type top cover layer provided on the one or more insulating layers at least above the ridge waveguide.

公开(公告)号：US20220011641A1

公开(公告)日：2022-01-13

申请号：US17348049

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Younghyun Kim ,  Didit Yudistira ,  Bernardette Kunert ,  Joris Van Campenhout ,  Maria Ioanna Pantouvaki

IPC: G02F1/225 ,  G02F1/21 ,  H01L29/94 ,  H01L29/66

Abstract: A monolithic integrated electro-optical phase modulator, a Mach-Zehnder modulator including one or more of the phase modulators, and method for fabricating the phase modulator by III-V-on-silicon semiconductor processing are provided. The phase modulator includes a silicon-based n-type substrate base layer, and a III-V n-type ridge waveguide for propagating light, wherein the ridge waveguide protrudes from and extends along the n-type substrate base layer. Further, the phase modulator includes one or more insulating layers provided on the ridge waveguide, wherein the one or more insulating layers have together a thickness of 1-100 nm, and a silicon-based p-type top cover layer provided on the one or more insulating layers at least above the ridge waveguide.

公开(公告)号：US11004962B2

公开(公告)日：2021-05-11

申请号：US16552468

申请日：2019-08-27

Applicant: IMEC vzw

Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L29/08 ,  H01L29/737 ,  H01L21/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

公开(公告)号：US10340188B2

公开(公告)日：2019-07-02

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/762 ,  H01L21/683 ,  H01L21/02

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US20210358748A1

公开(公告)日：2021-11-18

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L29/66

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US09614082B2

公开(公告)日：2017-04-04

申请号：US15208783

申请日：2016-07-13

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/78 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/785

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

公开(公告)号：US11655558B2

公开(公告)日：2023-05-23

申请号：US16996146

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer ,  Yves Mols ,  Marina Baryshnikova

IPC: C30B25/04 ,  C30B25/10 ,  C30B25/18 ,  C30B29/42 ,  C30B29/60 ,  H01L21/762 ,  H01L21/768

CPC classification number: C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/42 ,  C30B29/60 ,  H01L21/76224 ,  H01L21/76877

Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

公开(公告)号：US11195767B2

公开(公告)日：2021-12-07

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US10678007B2

公开(公告)日：2020-06-09

申请号：US16150898

申请日：2018-10-03

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Joris Van Campenhout ,  Bernardette Kunert ,  Maria Ioanna Pantouvaki ,  Dries Van Thourhout ,  Yuting Shi

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/13 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10

Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.

公开(公告)号：US20200075750A1

公开(公告)日：2020-03-05

申请号：US16552468

申请日：2019-08-27

Applicant: IMEC vzw

Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L29/737 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.