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    INTEGRATED CIRCUIT INCLUDING AT LEAST ONE NANO-RIDGE TRANSISTOR
    3.
    发明申请
    INTEGRATED CIRCUIT INCLUDING AT LEAST ONE NANO-RIDGE TRANSISTOR 审中-公开

    公开(公告)号：US20200075750A1

    公开(公告)日：2020-03-05

    申请号：US16552468

    申请日：2019-08-27

    Applicant: IMEC vzw

    Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

    IPC: H01L29/737 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

    Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

    Integrated circuit including at least one nano-ridge transistor
    4.
    发明授权
    Integrated circuit including at least one nano-ridge transistor 有权

    公开(公告)号：US11004962B2

    公开(公告)日：2021-05-11

    申请号：US16552468

    申请日：2019-08-27

    Applicant: IMEC vzw

    Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

    IPC: H01L29/08 ,  H01L29/737 ,  H01L21/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

    Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

    Nano-Ridge Engineering
    7.
    发明申请
    Nano-Ridge Engineering 有权

    公开(公告)号：US20210062360A1

    公开(公告)日：2021-03-04

    申请号：US16996146

    申请日：2020-08-18

    Applicant: IMEC VZW

    Inventor： Bernardette Kunert ,  Robert Langer ,  Yves Mols ,  Marina Baryshnikova

    IPC: C30B25/04 ,  H01L21/762 ,  H01L21/768 ,  C30B29/60 ,  C30B29/42 ,  C30B25/18 ,  C30B25/10

    Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

    Strained Group IV Channels
    9.
    发明申请
    Strained Group IV Channels 有权
    应变组IV通道

    公开(公告)号：US20170033183A1

    公开(公告)日：2017-02-02

    申请号：US15218922

    申请日：2016-07-25

    Applicant: IMEC VZW

    Inventor： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

    IPC: H01L29/10 ,  H01L29/04 ,  H01L29/161 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L21/324

    CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

    Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

    Abstract translation: 本文公开了一种半导体结构，其包括：（i）具有顶表面的单晶衬底，（ii）覆盖在单晶衬底上的非晶体结构，并且包括具有小于10微米的宽度的开口，并暴露部分顶部表面的 单晶衬底。 半导体结构还包括（iii）具有邻接部分的底表面的缓冲结构和每平方厘米具有小于108个穿透位错的顶表面，该缓冲结构由具有第一晶格常数的材料制成。 半导体结构还包括（iv）邻接缓冲结构的一个或多个IV族单晶结构，并且由具有与第一晶格常数不同的第二晶格常数的材料制成。

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