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    DATA STORAGE DEVICE WITH OPERATION BASED ON TEMPERATURE DIFFERENCE
    5.
    发明申请
    DATA STORAGE DEVICE WITH OPERATION BASED ON TEMPERATURE DIFFERENCE 审中-公开

    公开(公告)号：US20190043596A1

    公开(公告)日：2019-02-07

    申请号：US15838202

    申请日：2017-12-11

    Applicant: Intel Corporation

    Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

    IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/22

    Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT
    7.
    发明申请
    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT 有权

    公开(公告)号：US20210294698A1

    公开(公告)日：2021-09-23

    申请号：US17342993

    申请日：2021-06-09

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  George Kalwitz ,  Anand Ramalingam ,  Ravi Motwani ,  Renjie Chen

    IPC: G06F11/10 ,  H03M13/45 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

    Boosted bitlines for storage cell programmed state verification in a memory array
    8.
    发明授权
    Boosted bitlines for storage cell programmed state verification in a memory array 有权

    公开(公告)号：US11056203B1

    公开(公告)日：2021-07-06

    申请号：US16788194

    申请日：2020-02-11

    Applicant: INTEL CORPORATION

    Inventor： Xiang Yang ,  Pranav Kalavade ,  Ali Khakifirooz ,  Shantanu R. Rajwade ,  Sagar Upadhyay

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

    Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.

    Defective bit line management in connection with a memory access
    9.
    发明授权
    Defective bit line management in connection with a memory access 有权

    公开(公告)号：US10942799B1

    公开(公告)日：2021-03-09

    申请号：US16562745

    申请日：2019-09-06

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Ravi H. Motwani ,  Chang Wan Ha

    IPC: G06F11/07 ,  G11C16/34 ,  G11C7/12 ,  G11C29/44 ,  G11C16/14

    Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

    Program verification time reduction in non-volatile memory devices
    10.
    发明授权
    Program verification time reduction in non-volatile memory devices 有权

    公开(公告)号：US10832766B2

    公开(公告)日：2020-11-10

    申请号：US16146814

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Trupti Bemalkhedkar ,  Chang Wan Ha

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.

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