公开(公告)号：US20220110214A1

公开(公告)日：2022-04-07

申请号：US17550746

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Martin M. Chang ,  Tin Poay Chuah ,  Eng Huat Goh ,  Chu Aun Lim ,  Min Suet Lim

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/30

Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.

公开(公告)号：US20240234303A9

公开(公告)日：2024-07-11

申请号：US17972975

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20220181227A1

公开(公告)日：2022-06-09

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20160216731A1

公开(公告)日：2016-07-28

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

CPC classification number: G06F1/163 ,  G06F1/16 ,  G06F1/1656 ,  G06F1/187 ,  G06F13/38 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract translation: 实施例一般涉及利用计算机在包装结构上的装置。 计算机的一个实施例包括基板; 一个或多个半导体器件，所述一个或多个半导体器件是直接芯片附着到所述衬底，所述一个或多个半导体器件包括中央处理单元（CPU）; 以及安装在基板上的一个或多个附加部件，其中计算机不包括I / O部件。

公开(公告)号：US20240234234A9

公开(公告)日：2024-07-11

申请号：US17972923

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20240136279A1

公开(公告)日：2024-04-25

申请号：US17972975

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20240136243A1

公开(公告)日：2024-04-25

申请号：US17972923

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20190287872A1

公开(公告)日：2019-09-19

申请号：US15925429

申请日：2018-03-19

Applicant: INTEL CORPORATION

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US11929295B2

公开(公告)日：2024-03-12

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/82 ,  H01L2924/01029 ,  H01L2924/1811

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20230091395A1

公开(公告)日：2023-03-23

申请号：US17483670

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Mooi Ling Chang ,  Poh Boon Khoo ,  Chu Aun Lim ,  Min Suet Lim ,  Prabhat Ranjan

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.