公开(公告)号：US20240312991A1

公开(公告)日：2024-09-19

申请号：US18121720

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  David J. TOWNER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having tuned upper nanowires are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material.

公开(公告)号：US20230290852A1

公开(公告)日：2023-09-14

申请号：US17694170

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  David J. TOWNER ,  David N. GOLDSTEIN ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.

公开(公告)号：US20210408282A1

公开(公告)日：2021-12-30

申请号：US16912103

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Vishal TIWARI ,  Rishabh MEHANDRU ,  Dan S. LAVRIC ,  Michal MLECZKO ,  Szuya S. LIAO

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

公开(公告)号：US20240105804A1

公开(公告)日：2024-03-28

申请号：US17954194

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sean PURSEL ,  Dan S. LAVRIC ,  Allen B. GARDINER ,  Jonathan HINKE ,  Wonil CHUNG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/823431

Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.

公开(公告)号：US20230420531A1

公开(公告)日：2023-12-28

申请号：US17850769

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  Orb ACTON ,  David J. TOWNER ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/0673

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a first N-type dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the first N-type dipole material layer and a second N-type dipole material layer.

公开(公告)号：US20220093648A1

公开(公告)日：2022-03-24

申请号：US17030333

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/12 ,  H01L21/84

Abstract: Gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer over a second gate dielectric including the high-k dielectric layer on a second dipole material layer.

公开(公告)号：US20200219775A1

公开(公告)日：2020-07-09

申请号：US16631352

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Ying PANG ,  Florian GSTREIN ,  Dan S. LAVRIC ,  Ashish AGRAWAL ,  Robert NIFFENEGGER ,  Padmanava SADHUKHAN ,  Robert W. HEUSSNER ,  Joel M. GREGIE

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.

公开(公告)号：US20250098230A1

公开(公告)日：2025-03-20

申请号：US18370725

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Sean PURSEL ,  Dimitri KIOUSSIS ,  Lukas BAUMGARTEL ,  Mahdi AHMADI ,  Cortnie S. VOGELSBERG ,  Mengcheng LU ,  Omar Kyle HITE ,  Justin E. MUELLER ,  Lily Mao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having dual stress gates are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. An NMOS gate electrode is over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. A PMOS gate electrode is over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. The tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC: H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20240312996A1

公开(公告)日：2024-09-19

申请号：US18121724

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  Anand S. MURTHY ,  Mauro J. KOBRINSKY

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.