公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20240213331A1

公开(公告)日：2024-06-27

申请号：US18088542

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Pratik KOIRALA ,  Wesley HARRISON ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7838

Abstract: Gallium nitride (GaN) layer on substrate carburization for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer comprising silicon and carbon is above the substrate. A layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.

公开(公告)号：US20240213118A1

公开(公告)日：2024-06-27

申请号：US18088545

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Heli Chetanbhai VORA ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Thomas HOFF ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Paul NORDEEN ,  Nityan NAIR

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01P3/00

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01P3/003 ,  H01L2223/6627

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

公开(公告)号：US20240203978A1

公开(公告)日：2024-06-20

申请号：US18085116

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Harish KRISHNAMURTHY ,  Han Wui THEN ,  William J. LAMBERT ,  Jingshu YU

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based clamp structure is above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.

公开(公告)号：US20230097805A1

公开(公告)日：2023-03-30

申请号：US17485232

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a channel, where the channel comprises a first semiconductor material. In an embodiment, a source contact is at a first end of the channel, and a drain contact at a second end of the channel. In an embodiment, a gate electrode is between the source contact and the drain contact, and a field plate extends from the gate electrode towards the drain contact. In an embodiment, a plurality of protrusions extend out from the field plate towards the channel, where the protrusions comprise a second semiconductor material

公开(公告)号：US20190393332A1

公开(公告)日：2019-12-26

申请号：US16016411

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20190393210A1

公开(公告)日：2019-12-26

申请号：US16016396

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/06 ,  H01L29/872 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

公开(公告)号：US20190393041A1

公开(公告)日：2019-12-26

申请号：US16013860

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/778 ,  H01L29/66

Abstract: A transistor gate is disclosed. The transistor gate includes a first part above a substrate that has a first width and a second part above the first part that is centered with respect to the first part and that has a second width that is greater than the first width. The first part and the second part form a single monolithic T-gate structure.

公开(公告)号：US20190207003A1

公开(公告)日：2019-07-04

申请号：US16326857

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545

Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

公开(公告)号：US20190148533A1

公开(公告)日：2019-05-16

申请号：US16242949

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.