公开(公告)号：US12266712B2

公开(公告)日：2025-04-01

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H10B61/00 ,  H10B63/00 ,  H10N50/85 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：US20230411390A1

公开(公告)日：2023-12-21

申请号：US17842462

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Rachel A. Steinhardt ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci ,  Chelsey Dorow

IPC: H01L27/092 ,  H03K19/0185 ,  H01L29/26 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/092 ,  H03K19/018571 ,  H01L29/26 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5283

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

公开(公告)号：US20230197860A1

公开(公告)日：2023-06-22

申请号：US17560069

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Chelsey Dorow ,  Sudarat Lee ,  Kevin O'Brien ,  Ashish V. Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/4908

Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.

公开(公告)号：US20220199838A1

公开(公告)日：2022-06-23

申请号：US17133056

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching LIn ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/786 ,  H01L29/06 ,  H01L23/29 ,  H01L21/8238

Abstract: A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

公开(公告)号：US20250113599A1

公开(公告)日：2025-04-03

申请号：US18477414

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Wouter Mortelmans ,  Marko Radosavljevic ,  Uygar E. Avci ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/26 ,  H01L29/66 ,  H01L29/775

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

公开(公告)号：US12176388B2

公开(公告)日：2024-12-24

申请号：US16914137

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Shriram Shivaraman ,  Sudarat Lee ,  Tanay Gosavi ,  Chia-Ching Lin ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/04 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/267

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

公开(公告)号：US20240222428A1

公开(公告)日：2024-07-04

申请号：US18091206

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Kevin O'Brien ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Sudarat Lee ,  Ande Kitamura ,  Scott B. Clendenning ,  Mahmut Sami Kavrik

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/22 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/22 ,  H01L29/778 ,  H01L29/78696

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US20230099814A1

公开(公告)日：2023-03-30

申请号：US17485160

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kirby Maxey ,  Ashish Verma Penumatcha ,  Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Shriram Shivaraman ,  Tanay Gosavi ,  Uygar Avci

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66

Abstract: Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.