公开(公告)号：US20210399119A1

公开(公告)日：2021-12-23

申请号：US16910008

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Suresh VISHWANATH ,  Roza KOTLYAR ,  Han Wui THEN ,  Robert EHLERT ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Sandrine CHARUE-BAKKER

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.

公开(公告)号：US20190229264A1

公开(公告)日：2019-07-25

申请号：US16320010

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Roza KOTLYAR ,  Prashant MAJHI ,  Jeffery D. BIELEFELD

IPC: H01L45/00

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

公开(公告)号：US20160276440A1

公开(公告)日：2016-09-22

申请号：US15037296

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Roza KOTLYAR ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ian A. YOUNG

IPC: H01L29/12 ,  H01L29/205 ,  H01L29/165 ,  G11C5/06 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract translation: 本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在 沟道区域和设置在源区域和沟道区域的结点附近的异质袋。 异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧穿势垒，并且在施加到栅极的电压时在通道区中形成量子阱以增加通过TFET晶体管的电流 门高于阈值电压。

公开(公告)号：US20230116170A1

公开(公告)日：2023-04-13

申请号：US18070302

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Roza KOTLYAR ,  Rishabh MEHANDRU ,  Stephen CEA ,  Biswajeet GUHA ,  Dax CRUM ,  Tahir GHANI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

公开(公告)号：US20170054006A1

公开(公告)日：2017-02-23

申请号：US15118843

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Roza KOTLYAR ,  Ian A. YOUNG

IPC: H01L29/66 ,  H01L23/66 ,  G06F3/041 ,  H01L29/786

CPC classification number: H01L29/66977 ,  G06F3/041 ,  H01L21/18 ,  H01L23/66 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/88 ,  H01L2223/6677

Abstract: Described is a tunneling field effect transistor (TFET), comprising: a drain region having a first conductivity type; a source region having a second conductivity type opposite of the first conductivity type; a gate region to cause formation of a channel region between the source and drain regions; and a pocket disposed near a junction of the source region, wherein the pocket region formed from a material having lower percentage of one type of atom than percentage of the one type of atom in the source, channel, and drain regions.

Abstract translation: 描述了隧道场效应晶体管（TFET），其包括：具有第一导电类型的漏极区; 源区域，具有与第一导电类型相反的第二导电类型; 栅极区域，用于在源区和漏区之间形成沟道区; 以及设置在所述源极区域的接合点附近的口袋，其中所述口袋区域由具有比所述源极，沟道和漏极区域中的一种类型的原子的百分比低的一种类型的原子的比例低的材料形成。

公开(公告)号：US20160240671A1

公开(公告)日：2016-08-18

申请号：US14914847

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Benjamin CHU-KUNG ,  Roza KOTLYAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Abstract translation: 一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料 第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。 一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

公开(公告)号：US20160181424A1

公开(公告)日：2016-06-23

申请号：US14909981

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Rafael RIOS ,  Roza KOTLYAR ,  Kelin KUHN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/28512 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66795

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.

Abstract translation: 描述了利用设置在源极/漏极结构中的位错形成应变通道器件的方法。 这些方法/结构可以包括在器件的衬底中形成源极/漏极区域，以及在源极/漏极区域中形成合金，其中合金包括减小源极/漏极接触点与源极/漏极接触点之间的带隙的材料， 漏极区域基本上为零。 这里的实施例减小了器件的外部寄生电阻。

公开(公告)号：US20150072490A1

公开(公告)日：2015-03-12

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。