公开(公告)号：US20160379715A1

公开(公告)日：2016-12-29

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  Yogesh B. WAKCHAURE ,  Xin GUO ,  Paul D. RUBY ,  Justin R. DAYACAP ,  Joseph F. DOLLER ,  Robert E. FRICKEY

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract translation: 提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。 产生用于执行块擦除操作的一部分的命令。 在执行命令后至少执行一次读或写操作。 响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行命令的附加实例。

公开(公告)号：US20190103159A1

公开(公告)日：2019-04-04

申请号：US15720492

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Rohit S. SHENOY ,  Pranav KALAVADE ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

公开(公告)号：US20190243577A1

公开(公告)日：2019-08-08

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  David B. CARLTON ,  Mark Anthony GOLEZ ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Sagar S. SIDHPURA ,  Sagar UPADHYAY ,  Neelesh VEMULA ,  Yogesh B. WAKCHAURE ,  Ye ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US20190146669A1

公开(公告)日：2019-05-16

申请号：US16105363

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  David B. CARLTON ,  Xin GUO ,  Ryan J. NORTON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US20200027503A1

公开(公告)日：2020-01-23

申请号：US16586214

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  Xin GUO ,  Cole UHLMAN

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08

Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

公开(公告)号：US20200250028A1

公开(公告)日：2020-08-06

申请号：US16267323

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Naveen Prabhu VITTAL PRABHU ,  Bharat M. PATHAK ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  Violante MOSCHIANO ,  Walter DI FRANCESCO ,  Michele INCARNATI ,  Antonino Giuseppe LA SPINA

IPC: G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C16/10 ,  G11C11/56 ,  G06F11/07

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

公开(公告)号：US20190227749A1

公开(公告)日：2019-07-25

申请号：US16367638

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  David J. PELSTER ,  Donia SEBASTIAN ,  Curtis GITTENS ,  Xin GUO ,  Neelesh VEMULA ,  Varsha REGULAPATI ,  Naga Kiranmayee UPADHYAYULA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

公开(公告)号：US20180004410A1

公开(公告)日：2018-01-04

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  David B. CARLTON ,  Xin GUO ,  Ryan J. NORTON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.