公开(公告)号：US20220359194A1

公开(公告)日：2022-11-10

申请号：US17869524

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20240030032A1

公开(公告)日：2024-01-25

申请号：US18225030

申请日：2023-07-21

Applicant: Infineon Technologies AG

Inventor： Saurabh ROY ,  Ravi Keshav JOSHI ,  Hans-Joachim SCHULZE ,  Bernhard GOLLER ,  Daria KRASNOZHON

IPC: H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L21/268

CPC classification number: H01L21/0485 ,  H01L29/45 ,  H01L29/1608 ,  H01L21/268

Abstract: The present disclosure generally relates to a method of manufacturing a contact on a silicon carbide semiconductor substrate wherein the method comprises providing a 4H—SiC semiconductor substrate, irradiating a surface area of the 4H—SiC semiconductor substrate with a first thermal annealing laser beam, thereby generating a phase separation of the surface area comprising at least a 3C—SiC layer, and depositing a contact material onto the 3C—SiC layer to form a contact layer on the semiconductor substrate. The disclosure further relates to a silicon carbide semiconductor device with an Ohmic contact comprising a 4H—SiC semiconductor substrate, a 3C—SiC layer, and a contact layer directly in contact with the 3C—SiC layer at the semiconductor surface.

公开(公告)号：US20200286730A1

公开(公告)日：2020-09-10

申请号：US16811192

申请日：2020-03-06

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/475 ,  H01L21/4757

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20210253421A1

公开(公告)日：2021-08-19

申请号：US17248799

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Andre BROCKMEIER ,  Markus BERGMEISTER ,  Bernhard GOLLER ,  Daniel PIEBER ,  Sokratis SGOURIDIS

IPC: B81C1/00

Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.

公开(公告)号：US20170259354A1

公开(公告)日：2017-09-14

申请号：US15065914

申请日：2016-03-10

Applicant: Infineon Technologies AG

Inventor： Ingo MURI ,  Alexander BINTER ,  Bernhard GOLLER ,  Christian GRINDLING

IPC: B23C3/13 ,  H01L21/304 ,  H01L21/67 ,  B23Q3/08 ,  H01L21/683

CPC classification number: B23C3/13 ,  B23Q3/088 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6838 ,  H01L21/6875 ,  H01L21/68757 ,  Y10T279/11 ,  Y10T409/3042

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including a support carrier; and a workpiece-support replaceably mounted on the support carrier; and a planarization tool configured to planarize the at least one portion of the workpiece-support and to planarize one or more workpieces on the at least one portion of the workpiece-support.

公开(公告)号：US20240153759A1

公开(公告)日：2024-05-09

申请号：US18407025

申请日：2024-01-08

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/467 ,  H01L21/475 ,  H01L21/4757 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L21/02203 ,  H01L21/0203 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/467 ,  H01L21/475 ,  H01L21/47576 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20230238442A1

公开(公告)日：2023-07-27

申请号：US18097656

申请日：2023-01-17

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Romain ESTEVE ,  Saurabh ROY ,  Bernhard GOLLER ,  Werner SCHUSTEREDER ,  Kristijan Luka MLETSCHNIG

IPC: H01L29/45 ,  H01L29/417 ,  H01L23/528 ,  H01L29/40 ,  H01L21/321

CPC classification number: H01L29/45 ,  H01L29/41741 ,  H01L23/528 ,  H01L29/401 ,  H01L21/321

Abstract: A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.

公开(公告)号：US20170263490A1

公开(公告)日：2017-09-14

申请号：US15446059

申请日：2017-03-01

Applicant: Infineon Technologies AG

Inventor： Ingo MURI ,  Alexander BINTER ,  Bernhard GOLLER ,  Christian GRINDLING

IPC: H01L21/683 ,  B23C3/13 ,  H01L21/67 ,  B23Q3/08

CPC classification number: H01L21/6838 ,  B23C3/13 ,  B23Q3/088 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6875 ,  H01L21/68757 ,  Y10T279/11 ,  Y10T409/303808 ,  Y10T409/30868

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including at least one portion configured to support one or more workpieces; and a planarization tool configured to planarize the at least one portion of the chuck and to planarize one or more workpieces on the at least one portion of the chuck; wherein the at least one portion of the chuck includes at least one of particles, pores and/or a polymer.