公开(公告)号：US20200286730A1

公开(公告)日：2020-09-10

申请号：US16811192

申请日：2020-03-06

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/475 ,  H01L21/4757

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20170059997A1

公开(公告)日：2017-03-02

申请号：US15249758

申请日：2016-08-29

Applicant: Infineon Technologies AG

Inventor： Roland RUPP ,  Rudolf ELPELT ,  Romain ESTEVE

IPC: G03F7/20 ,  H01L21/027 ,  H01L29/06 ,  H01L23/544 ,  H01L29/16 ,  H01L29/36

CPC classification number: G03F7/70008 ,  G03F7/70775 ,  H01J37/3171 ,  H01L21/0273 ,  H01L21/0465 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8611 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A beam modifier device is provided that includes scattering portions in which particles vertically impinging on an exposure surface of the beam modifier device are deflected from a vertical direction. A total permeability for the particles changes along a lateral direction parallel to the exposure surface.

Abstract translation: 提供了一种光束调节装置，其包括散射部分，其中垂直撞击在光束修改装置的曝光表面上的颗粒从垂直方向偏转。 颗粒的总磁导率沿平行于曝光表面的横向变化。

公开(公告)号：US20180175153A1

公开(公告)日：2018-06-21

申请号：US15848614

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim SCHULZE ,  Guenther RUHL ,  Roland RUPP

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/456 ,  C01B32/184 ,  C01B2204/04 ,  H01L21/28525 ,  H01L29/1606 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/452 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: A semiconductor device includes a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate. Additionally, the semiconductor device includes a graphene layer portion located adjacent to at least a portion of the transistor doping region at a surface of the semiconductor substrate. The semiconductor device further includes a transistor wiring structure located adjacent to the graphene layer portion.

公开(公告)号：US20160155714A1

公开(公告)日：2016-06-02

申请号：US14555736

申请日：2014-11-28

Applicant: Infineon Technologies AG

Inventor： Jochen HILSENBECK ,  Jens Peter KONRATH ,  Thomas FRANK ,  Roland RUPP

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3121 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/4238 ,  H01L29/43 ,  H01L29/7392 ,  H01L29/7396 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/8083 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/45124 ,  H01L2924/01014 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/3512

Abstract: According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

Abstract translation: 根据各种实施例，半导体器件可以包括：形成在半导体器件的表面处的层堆叠，所述层堆叠包括：包括第一金属或金属合金的金属化层; 覆盖金属化层的保护层，保护层包括第二金属或金属合金，其中第二金属或金属合金比第一金属或金属合金低。

公开(公告)号：US20190049850A1

公开(公告)日：2019-02-14

申请号：US16153186

申请日：2018-10-05

Applicant: Infineon Technologies AG

Inventor： Roland RUPP ,  Rudolf ELPELT ,  Romain ESTEVE

IPC: G03F7/20 ,  H01L29/36 ,  H01L29/66 ,  H01L23/544 ,  H01L29/16 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06

Abstract: A semiconductor device is provided that includes a silicon carbide substrate including a main surface at which a plurality of doped zones are formed in a junction termination extension zone of the silicon carbide substrate, the plurality of doped zones are arranged such that a lateral dopant concentration gradient is formed that decreases from a central region of the silicon carbide substrate to an outer edge region of the silicon carbide substrate.

公开(公告)号：US20180086630A1

公开(公告)日：2018-03-29

申请号：US15716538

申请日：2017-09-27

Applicant: Infineon Technologies AG

Inventor： Andre BROCKMEIER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0027 ,  B81B3/0097 ,  B81B2203/0118 ,  B81C1/00349 ,  B81C1/00357 ,  B81C2201/0192

Abstract: In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.

公开(公告)号：US20220359194A1

公开(公告)日：2022-11-10

申请号：US17869524

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20200381256A1

公开(公告)日：2020-12-03

申请号：US16884442

申请日：2020-05-27

Applicant: Infineon Technologies AG

Inventor： Francisco Javier SANTOS RODRIGUEZ ,  Roland RUPP ,  Hans-Joachim SCHULZE

IPC: H01L21/268 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.

公开(公告)号：US20240153759A1

公开(公告)日：2024-05-09

申请号：US18407025

申请日：2024-01-08

Applicant: Infineon Technologies AG

Inventor： Iris MODER ,  Bernhard GOLLER ,  Tobias Franz Wolfgang HOECHBAUER ,  Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/02 ,  H01L21/467 ,  H01L21/475 ,  H01L21/4757 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L21/02203 ,  H01L21/0203 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/467 ,  H01L21/475 ,  H01L21/47576 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20170207124A1

公开(公告)日：2017-07-20

申请号：US15404400

申请日：2017-01-12

Applicant: Infineon Technologies AG

Inventor： Roland RUPP ,  Francisco Javier SANTOS RODRIGUEZ ,  Hans-Joachim SCHULZE

IPC: H01L21/78 ,  H01L29/66 ,  H01L21/322 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/7806 ,  H01L21/02002 ,  H01L21/265 ,  H01L21/268 ,  H01L21/322 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/8611

Abstract: Methods of forming a semiconductor device are provided. A method includes introducing impurities into a part of a semiconductor substrate at a first surface of the semiconductor substrate by ion implantation, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate. The method further includes forming a semiconductor layer on the first surface of the semiconductor substrate. The method further includes irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate local damage of a crystal lattice of the semiconductor substrate. The method further includes separating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, where the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical stress.