公开(公告)号：US20200035645A1

公开(公告)日：2020-01-30

申请号：US16523789

申请日：2019-07-26

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Frank Daeche

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13

Abstract: A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.

公开(公告)号：US11632860B2

公开(公告)日：2023-04-18

申请号：US16663947

申请日：2019-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Martin Benisek ,  Liu Chen ,  Frank Daeche ,  Josef Maerz

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

公开(公告)号：US11004823B2

公开(公告)日：2021-05-11

申请号：US16523789

申请日：2019-07-26

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Frank Daeche

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/13

Abstract: A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.

公开(公告)号：US20230282553A1

公开(公告)日：2023-09-07

申请号：US18315787

申请日：2023-05-11

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Frank Daeche ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49537 ,  H01L23/49524 ,  H01L24/33 ,  H01L21/4842 ,  H01L24/97 ,  H01L24/83 ,  H05K1/185 ,  H01L21/4825 ,  H01L2224/83385 ,  H01L23/49513 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L24/05 ,  H01L2224/05647 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/83815 ,  H01L2224/83203 ,  H05K3/0035

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

公开(公告)号：US20230240012A1

公开(公告)日：2023-07-27

申请号：US18122988

申请日：2023-03-17

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Martin Benisek ,  Liu Chen ,  Frank Daeche ,  Josef Maerz

IPC: H05K1/18 ,  H05K1/03 ,  H05K1/02

CPC classification number: H05K1/181 ,  H05K1/021 ,  H05K1/0298 ,  H05K1/0306

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

公开(公告)号：US11562967B2

公开(公告)日：2023-01-24

申请号：US17208363

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Frank Daeche

IPC: H01L23/538 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: A method for fabricating a semiconductor package includes: providing a semiconductor wafer having opposing first and second sides, the semiconductor wafer being arranged on a first carrier such that the second side of the wafer faces the carrier; masking sawing lines on the first side of the semiconductor wafer with a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying or by high velocity oxygen fuel spraying or by cold plasma assisted deposition, such that the first metal layer does not cover the sawing lines, the deposited first metal layer having a thickness of 50 μm or more; singulating the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the sawing lines; and encapsulating the plurality of semiconductor dies with an encapsulant such that the first metal layer is exposed on a first side of the encapsulant.

公开(公告)号：US20170271260A1

公开(公告)日：2017-09-21

申请号：US15459270

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Frank Daeche ,  Zeeshan Umar

IPC: H01L23/522 ,  H02M3/158 ,  H01L23/552

CPC classification number: H01L23/5227 ,  H01F17/00 ,  H01F17/0013 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2924/181 ,  H02M3/158 ,  H01L2924/00012

Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.

公开(公告)号：US11903132B2

公开(公告)日：2024-02-13

申请号：US18122988

申请日：2023-03-17

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Martin Benisek ,  Liu Chen ,  Frank Daeche ,  Josef Maerz

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/181 ,  H05K1/021 ,  H05K1/0298 ,  H05K1/0306

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

公开(公告)号：US11699640B2

公开(公告)日：2023-07-11

申请号：US17353047

申请日：2021-06-21

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Frank Daeche ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H05K1/18 ,  H05K3/00

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4842 ,  H01L23/49524 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H05K1/185 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83815 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

公开(公告)号：US20220406692A1

公开(公告)日：2022-12-22

申请号：US17353047

申请日：2021-06-21

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Frank Daeche ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.