公开(公告)号：US20190096798A1

公开(公告)日：2019-03-28

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/40 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20240006286A1

公开(公告)日：2024-01-04

申请号：US17856795

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Arghya Sain ,  Sujit Sharan ,  Hoai V. Le ,  Jianyong Xie

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/15 ,  H01L24/16 ,  H01L2224/16235

Abstract: A substrate comprising a core structure between a first metallization stack and a second metallization stack. A hardware interface is at a side of the second metallization stack. A first interconnect comprises both a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack. The first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A second interconnect comprises both a second via portion, and a second trace portion which extends from the second via portion in the first routing layer. The second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A first multi-layer insulator structure adjoins respective sides of the first and second trace portions.

公开(公告)号：US11869842B2

公开(公告)日：2024-01-09

申请号：US16521435

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Arghya Sain ,  Sri Chaitra Jyotsna Chavali ,  Lijiang Wang ,  Cemil Geyik

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

公开(公告)号：US11705390B2

公开(公告)日：2023-07-18

申请号：US16366034

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Arghya Sain

IPC: H01L23/66 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638

Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

公开(公告)号：US20210296241A1

公开(公告)日：2021-09-23

申请号：US16825261

申请日：2020-03-20

Applicant: Intel Corporation

Inventor： Arghya Sain ,  Lesley A. Polka Wood ,  Russell K. Mortensen

IPC: H01L23/538 ,  H01L23/498

Abstract: Embodiments may relate to a microelectronic package that includes an active die at a first side of the substrate and an interconnect at a second side of the substrate. A high-speed input/output (HSIO) die may also be coupled with the first side of substrate. The HSIO die may be coupled with the active die by a bridge. Other embodiments may be described or claimed.

公开(公告)号：US20240088047A1

公开(公告)日：2024-03-14

申请号：US18516579

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Arghya Sain ,  Sri Chaitra Jyotsna Chavali ,  Lijiang Wang ,  Cemil Geyik

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

公开(公告)号：US20230299044A1

公开(公告)日：2023-09-21

申请号：US17698928

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Arghya Sain ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3025 ,  H01L2225/06537 ,  H01L2225/06586

Abstract: In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.

公开(公告)号：US10475736B2

公开(公告)日：2019-11-12

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.